forked from M-Labs/zynq-rs
slcr: remove soft reset
Does not work and probably difficult to get to work.
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parent
6fa3a6bbd9
commit
0c60d684e4
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@ -265,14 +265,6 @@ impl RegisterBlock {
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r
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r
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}
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}
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/// Perform a soft reset
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pub fn soft_reset(&mut self) {
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self.pss_rst_ctrl.write(
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PssRstCtrl::zeroed()
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.soft_rst(true)
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);
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}
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pub fn init_preload_fpga(&mut self) {
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pub fn init_preload_fpga(&mut self) {
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// Assert FPGA top level output resets
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// Assert FPGA top level output resets
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self.fpga_rst_ctrl.write(
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self.fpga_rst_ctrl.write(
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@ -8,7 +8,6 @@ pub unsafe extern "C" fn PrefetchAbort() {
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println!("PrefetchAbort");
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println!("PrefetchAbort");
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slcr::RegisterBlock::unlocked(|slcr| slcr.soft_reset());
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loop {}
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loop {}
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}
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}
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@ -20,6 +19,5 @@ pub unsafe extern "C" fn DataAbort() {
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println!("DataAbort on core {}", MPIDR.read() & CORE_MASK);
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println!("DataAbort on core {}", MPIDR.read() & CORE_MASK);
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println!("DFSR: {:03X}", DFSR.read());
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println!("DFSR: {:03X}", DFSR.read());
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slcr::RegisterBlock::unlocked(|slcr| slcr.soft_reset());
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loop {}
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loop {}
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}
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}
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@ -14,6 +14,5 @@ fn panic(info: &core::panic::PanicInfo) -> ! {
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println!("");
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println!("");
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}
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}
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slcr::RegisterBlock::unlocked(|slcr| slcr.soft_reset());
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loop {}
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loop {}
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}
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}
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