f340cd9380
add support to not compile with dummy FIQ handler
298f64a2f9
boot: enable FIQ
0cf28a92fd
add support to not compile with dummy FIQ handler
c5e6deb44a
boot: enable FIQ on reset
4168eb63a7
GIC: fix wrong core target config when enabling interrupt (#109)
a43b8bf64e
mkbootimage: work around buffer overflow
91bae572f9
fix "unknown argument '-Wl,--undefined=AUDITABLE_VERSION_INFO'"
6f475e5c20
replace old example and update performance docs
547a02e6d3
sim: add step input to gtx
39bb656f85
sim: replace beating period error formula
5a9fa937ee
sim: refactor into OOP & add FW collector
f7a1d17628
notebook: convert all ipynb to py scripts
kasli & kasli-soc: describe mounting fan onto heatsink
bcb3faf080
kasli: describe mounting fan onto heatsink
074c9153c7
kasli-soc: describe mounting fan onto heatsink
fastino: add zero voltage output failure mode
Kasli-soc: add WRPLL clock recovery
Force push to address above comments, add an I term for main PLL, improve deglitcher, general clean up and update commit messages. Ready to review.
2f57ccf617
WRPLL firmware
05f80b579f
Si549 firmware
dbfb420212
WRPLL gateware
d13800dca8
si549 gateware
7dc57dc24e
WRPLL firmware
6a47c2fcf2
Si549 firmware
b9251c0b26
WRPLL gateware
c761958816
si549 gateware
Kasli-soc: add WRPLL clock recovery
I tried moving the gateware collector to firmware with a gtx & main tag interrupts setup. But the CPU is not fast enough to sample two consecutive gtx tags while executing the helper PLL + main…
satellite: add WRPLL clock recovery
0a4c34b1f2
WRPLL firmware
e592a69537
Si549 firmware
0cd1ac9204
WRPLL gateware
e08d942066
si549 gateware