@@ -0,0 +72,4 @@
+        ]
+
+
+class Collector(Module):

@@ -206,3 +208,3 @@
 
 class GenericMaster(SoCCore):
-    def __init__(self, description, acpki=False):
+    def __init__(self, description, acpki=False, si5324=False):

@@ -13,2 +13,4 @@
 }
 
+#[cfg(has_si549)]
+const USE_SI549: u8 = 0xFF;

@@ -0,0 +1,551 @@
+use core::result::Result::Ok;

@@ -0,0 +291,4 @@
+    static M_INTEGRATOR: Mutex<i32> = Mutex::new(0);
+
+    #[derive(Clone, Copy)]
+    pub enum FIQ {

@@ -0,0 +691,4 @@
+    fn one_clock_cycle(timer: &mut GlobalTimer) {
+        unsafe {
+            csr::wrpll_refclk::mmcm_dclk_write(1);
+            timer.delay_us(1);

@@ -47,6 +48,19 @@ eem_iostandard_dict = {
 def eem_iostandard(eem):
     return IOStandard(eem_iostandard_dict[eem])
 
+class ClockSynthesis(Module):

@@ -0,0 +133,4 @@
+            )
+        ]
+
+        # PL->PS interrupt

@@ -0,0 +304,4 @@
+            csr::wrpll::main_dcxo_adpll_stb_write(1);
+            csr::wrpll::main_dcxo_adpll_stb_write(0);
+
+            if csr::wrpll::main_dcxo_nack_read() == 1 {

@@ -0,0 +302,4 @@
+            csr::wrpll::main_dcxo_adpll_write(adpll as u32);
+
+            csr::wrpll::main_dcxo_adpll_stb_write(1);
+            csr::wrpll::main_dcxo_adpll_stb_write(0);

@@ -0,0 +364,4 @@
+        static REF_TAG: Mutex<u32> = Mutex::new(0);
+        static REF_TAG_READY: Mutex<bool> = Mutex::new(false);
+        static MAIN_TAG: Mutex<u32> = Mutex::new(0);
+        static MAIN_TAG_READY: Mutex<bool> = Mutex::new(false);

@@ -0,0 +650,4 @@
+
+            info!("warming up refclk...");
+            // refclk need a couple seconds for freq counter to read it properly
+            timer.delay_us(20_000_000);

@@ -0,0 +799,4 @@
+
+            let locked = unsafe { csr::wrpll_refclk::mmcm_locked_read() == 1 };
+            if !locked {
+                return Err("mmcm failed to generate 125Mhz ref clock from SMA CLKIN");