forked from M-Labs/zynq-rs
morgan
4168eb63a7
# Summary - Before the patch, an extra 1 is added to `target_cpu` and the interrupt will be configured to the wrong CPU target. | target_cpu | bits set before patch | bits set after patch | | -----------| ----------- | ----------- | | core0 | 0b10 (enable interrupt on core1) | 0b01 (enable interrupt on core0) | | core1 | 0b11 (enable interrupt on core0 & core1)| 0b10 (enable interrupt on core1) | - [Correct ICDIPTR Register configuration from AMD](https://docs.xilinx.com/r/en-US/ug585-zynq-7000-SoC-TRM/Software-Generated-Interrupts-SGI?tocId=0TsxAmy8MHRPDsayG96K1Q) Reviewed-on: M-Labs/zynq-rs#109 Co-authored-by: morgan <mc@m-labs.hk> Co-committed-by: morgan <mc@m-labs.hk> |
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| .. | ||
| clocks | ||
| ddr | ||
| devc | ||
| eth | ||
| i2c | ||
| ps7_init | ||
| sdio | ||
| timer | ||
| uart | ||
| axi_gp.rs | ||
| axi_hp.rs | ||
| error_led.rs | ||
| gic.rs | ||
| lib.rs | ||
| logger.rs | ||
| mpcore.rs | ||
| slcr.rs | ||
| stdio.rs | ||
| time.rs | ||