forked from M-Labs/zynq-rs
morgan
4168eb63a7
# Summary - Before the patch, an extra 1 is added to `target_cpu` and the interrupt will be configured to the wrong CPU target. | target_cpu | bits set before patch | bits set after patch | | -----------| ----------- | ----------- | | core0 | 0b10 (enable interrupt on core1) | 0b01 (enable interrupt on core0) | | core1 | 0b11 (enable interrupt on core0 & core1)| 0b10 (enable interrupt on core1) | - [Correct ICDIPTR Register configuration from AMD](https://docs.xilinx.com/r/en-US/ug585-zynq-7000-SoC-TRM/Software-Generated-Interrupts-SGI?tocId=0TsxAmy8MHRPDsayG96K1Q) Reviewed-on: M-Labs/zynq-rs#109 Co-authored-by: morgan <mc@m-labs.hk> Co-committed-by: morgan <mc@m-labs.hk> |
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|---|---|---|
| .cargo | ||
| experiments | ||
| libasync | ||
| libboard_zynq | ||
| libconfig | ||
| libcortex_a9 | ||
| libregister | ||
| libsupport_zynq | ||
| openocd | ||
| szl | ||
| .gitignore | ||
| Cargo.lock | ||
| Cargo.toml | ||
| LICENSE | ||
| README.md | ||
| armv7-none-eabihf.json | ||
| flake.lock | ||
| flake.nix | ||
| fsbl.patch | ||
| kasli_soc_por.py | ||
| remote_run.sh | ||
README.md
Bare-metal Rust on Zynq-7000
Supported features:
- Clocking setup
- UART
- SDRAM setup
- Ethernet with smoltcp and async-await on TCP sockets
- SD card
- PL programming and startup
- Pure Rust SZL first-stage bootloader, with SD boot and netboot
- Control of second CPU core and message passing, with async-await support
Supported boards:
- Kasli-SoC
- ZC706
- Red Pitaya
- Cora Z7-10 (seems to also run on Cora Z7-07S, including dual-core support)
Build
Zynq-rs is packaged using the Nix Flakes system. Install Nix 2.4+ and enable flakes by adding experimental-features = nix-command flakes to nix.conf (e.g. ~/.config/nix/nix.conf).
You can build SZL or experiments crate for the platform of your choice by using nix build command, e.g.
nix build .#coraz7-experiments
Alternatively, you can still use cargo xbuild within nix develop shell.
nix develop
cargo xbuild --release -p experiments
Currently the ELF output is placed at target/armv7-none-eabihf/release/experiments, or result/experiments.elf for Nix Flakes build.
Debug
Running on the ZC706
nix develop
cargo xbuild --release -p experiments
cd openocd
openocd -f zc706.cfg
Running on the Cora Z7-10
nix develop
cargo xbuild --release -p experiments --no-default-features --features=target_coraz7
cd openocd
openocd -f cora-z7-10.cfg
Loading a bitstream into volatile memory
openocd -f zc706.cfg -c "pld load 0 blinker_migen.bit; exit"
License
Copyright (C) 2019-2022 M-Labs Limited. Released under the GNU LGPL v3. See the LICENSE file for details.