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Bare-metal Rust on Zynq-7000
636 Commits 5 Branches 0 Tags 1.5 MiB
Rust 90.6%
Nix 6.8%
Assembly 2.5%
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morgan 4168eb63a7 GIC: fix wrong core target config when enabling interrupt (#109) 
# Summary

- Before the patch, an extra 1 is added to `target_cpu` and the interrupt will be configured to the wrong CPU target.

| target_cpu | bits set before patch | bits set after patch   |
| -----------| -----------                      | -----------                       |
| core0      | 0b10 (enable interrupt on core1) | 0b01 (enable interrupt on core0)  |
| core1      | 0b11 (enable interrupt on core0 & core1)| 0b10 (enable interrupt on core1) |

- [Correct ICDIPTR Register configuration from AMD](https://docs.xilinx.com/r/en-US/ug585-zynq-7000-SoC-TRM/Software-Generated-Interrupts-SGI?tocId=0TsxAmy8MHRPDsayG96K1Q)

Reviewed-on: M-Labs/zynq-rs#109
Co-authored-by: morgan <mc@m-labs.hk>
Co-committed-by: morgan <mc@m-labs.hk>
2023-12-19 18:41:03 +08:00
.cargo cargo: remove unmaintained runner 2020-09-09 15:01:39 +08:00
experiments libcortex_a9: add interrupt exit support for interrupt_handler macro (#107) 2023-11-20 12:30:27 +08:00
libasync libasync: provide get/set ack_delay (new in smoltcp 0.7.0) 2021-02-08 03:06:51 +01:00
libboard_zynq GIC: fix wrong core target config when enabling interrupt (#109) 2023-12-19 18:41:03 +08:00
libconfig config: add "fat_lfn" feature 2022-04-07 15:44:07 +08:00
libcortex_a9 libcortex_a9: add interrupt exit support for interrupt_handler macro (#107) 2023-11-20 12:30:27 +08:00
libregister libregister: allow rustdoc for register! macro 2020-11-19 20:26:18 +01:00
libsupport_zynq panic: turn on error_led for kasli_soc 2022-08-26 17:22:42 +08:00
openocd openocd: moved common code from target files 2022-03-10 17:05:25 +08:00
szl szl: change CPU frequency of Kasli-SoC to 1 GHz 2022-07-20 15:16:15 +08:00
.gitignore nix flakes support (#85) 2022-01-27 16:26:33 +08:00
armv7-none-eabihf.json define custom target, use with cargo-xbuild 2019-08-06 22:03:04 +02:00
Cargo.lock update dependencies 2022-03-10 17:01:37 +08:00
Cargo.toml Kasli-SoC: Get MAC address from EEPROM (#90) 2022-03-07 18:01:44 +08:00
flake.lock switch to new nixpkgs release 2023-12-03 10:45:47 +08:00
flake.nix mkbootimage: work around buffer overflow 2023-12-03 16:16:22 +08:00
fsbl.patch nix flakes support (#85) 2022-01-27 16:26:33 +08:00
kasli_soc_por.py add Kasli-SoC POR control program 2021-05-29 17:43:21 +08:00
LICENSE LGPLv3 2021-04-06 16:46:38 +08:00
README.md update copyright year 2022-01-27 18:00:24 +08:00
remote_run.sh remote_run.sh: clean up getopts 2020-11-18 17:45:43 +08:00

README.md

Bare-metal Rust on Zynq-7000

Supported features:

  • Clocking setup
  • UART
  • SDRAM setup
  • Ethernet with smoltcp and async-await on TCP sockets
  • SD card
  • PL programming and startup
  • Pure Rust SZL first-stage bootloader, with SD boot and netboot
  • Control of second CPU core and message passing, with async-await support

Supported boards:

  • Kasli-SoC
  • ZC706
  • Red Pitaya
  • Cora Z7-10 (seems to also run on Cora Z7-07S, including dual-core support)

Build

Zynq-rs is packaged using the Nix Flakes system. Install Nix 2.4+ and enable flakes by adding experimental-features = nix-command flakes to nix.conf (e.g. ~/.config/nix/nix.conf).

You can build SZL or experiments crate for the platform of your choice by using nix build command, e.g.

nix build .#coraz7-experiments

Alternatively, you can still use cargo xbuild within nix develop shell.

nix develop
cargo xbuild --release -p experiments

Currently the ELF output is placed at target/armv7-none-eabihf/release/experiments, or result/experiments.elf for Nix Flakes build.

Debug

Running on the ZC706

nix develop
cargo xbuild --release -p experiments
cd openocd
openocd -f zc706.cfg

Running on the Cora Z7-10

nix develop
cargo xbuild --release -p experiments --no-default-features --features=target_coraz7
cd openocd
openocd -f cora-z7-10.cfg

Loading a bitstream into volatile memory

openocd -f zc706.cfg -c "pld load 0 blinker_migen.bit; exit"

License

Copyright (C) 2019-2022 M-Labs Limited. Released under the GNU LGPL v3. See the LICENSE file for details.