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zynq-rs
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Code Pull Requests Activity
300 Commits 5 Branches 0 Tags 1.4 MiB
Commit Graph

300 Commits

Author SHA1 Message Date
Astro f07a541c99 eth: model rx/tx state with type parameters 2019-06-09 20:10:41 +02:00
Astro 74bd81f87f eth: add safety asserts 2019-06-09 02:23:37 +02:00
Astro 824e91e6cb eth: rx/tx desc list, start_rx 2019-06-09 01:02:10 +02:00
Astro 2d7fed6c59 link again compiler_builtins 
required for memset etc
 2019-06-09 01:00:58 +02:00
Astro d447f1cc45 main: probe for PHYs 2019-06-04 23:50:11 +02:00
Astro b9ca9324f0 eth: fix initialization 2019-06-04 23:48:33 +02:00
Astro 6d15b82a3e cortex_a9::regs: init U bit for unaligned access 2019-06-04 23:47:23 +02:00
Astro acf995d7da soft_reset: rm unreachable! 2019-05-31 00:19:20 +02:00
Astro bf4f5108f4 main: add UART_RATE 2019-05-31 00:19:01 +02:00
Astro 2f27ff574f improve linker script 2019-05-31 00:17:53 +02:00
Astro 2df74cc055 add static exception handling 2019-05-30 20:30:19 +02:00
Astro b13bf72c17 eth: begin phy communication 2019-05-30 02:42:42 +02:00
Astro 5b15bb5c0a main: make boot_core0() naked 2019-05-30 02:41:44 +02:00
Astro c0610ad66a slcr: init gem* rclk/clk 2019-05-30 02:26:19 +02:00
Astro ee7ae7f7cc slcr: add soft_rst() 2019-05-30 00:24:51 +02:00
Astro b961526b97 uart: remove type conversion from baud_rate_gen 2019-05-30 00:22:45 +02:00
Astro a645d13f4b add uart panic handler 2019-05-28 00:28:35 +02:00
Astro 75bb755327 extend linker script 2019-05-27 22:38:10 +02:00
Astro d10ffe9eb9 eth: setup mio_pins, configure net_cfg 2019-05-25 03:06:39 +02:00
Astro 51c39f032e run with the cora z7-10 2019-05-25 02:38:48 +02:00
Astro b3da0e4c93 slcr: define all mio_pin regs, typed io_type 2019-05-25 02:34:58 +02:00
Astro 6bf210366a regs: properly emit doc_comments 2019-05-24 23:49:49 +02:00
Astro 56c2f1d833 eth: add net_status, phy_maint registers 2019-05-24 00:20:59 +02:00
Astro ad77e3dc04 eth: add net_cfg register 2019-05-24 00:06:29 +02:00
Astro 402b8c9ab1 eth: no unsafe, note, add qbar register fields 2019-05-23 23:18:36 +02:00
Astro 1033648c3e add l1_cache_init() 2019-05-23 19:05:06 +02:00
Astro 179c617904 add register_bits_typed! macro 2019-05-23 18:29:05 +02:00
Astro 785e726661 RegisterW/RegisterRW: required &mut self for safety 2019-05-23 18:01:18 +02:00
Astro 62ca26fa71 slcr: abstract with RegisterBlock 2019-05-23 17:52:06 +02:00
Astro fd7fd0db14 main: rm unused feature #![feature(global_asm)] 2019-05-23 16:06:41 +02:00
Astro 99371375fd Cargo.toml: don't disable lto for profile.release 2019-05-23 16:06:17 +02:00
Astro ea62d4fdec uart: make baudrate configurable, run at 115,200 baud 2019-05-23 15:50:53 +02:00
Astro 15883293ac uart: use div_round_closest in baud_rate_gen 2019-05-23 15:37:07 +02:00
Astro 7428fec200 uart: add more channel_sts flags, wait for tx_fifo_empty() before sending 2019-05-23 15:36:34 +02:00
Astro 673d585d2f uart: extend regs 2019-05-22 01:42:24 +02:00
Astro b296fc1d7f uart: add baud_rate_gen 2019-05-22 01:42:00 +02:00
Astro 43b6d3acd0 uart: wait for reset 2019-05-21 02:53:59 +02:00
Astro 47ec0116a9 use uart1 with more configuration 2019-05-21 01:30:54 +02:00
Astro 5d02fe5c95 slcr: with_slcr() for unlock/lock 2019-05-21 01:30:17 +02:00
Astro 351d18c10f add register_at! macro 2019-05-20 23:01:50 +02:00
Astro 7e12468bf2 README 2019-05-20 01:21:48 +02:00
Astro c88374eab1 fix SP init 2019-05-20 01:21:22 +02:00
Astro b754581452 eth: add regs and init 2019-05-07 19:28:33 +02:00
Astro 7872e00182 uart: move logic outside regs 2019-05-07 17:46:37 +02:00
Astro 275f297309 uart: impl fmt::Write 2019-05-07 16:45:31 +02:00
Astro ca9b10dce8 refactor regs macros for RO/WO/RW access 2019-05-07 00:32:45 +02:00
Astro 1e540a1175 replace #[repr(packed)] with #[repr(C)] 
avoids warnings regarding unsafe behaviour
 2019-05-07 00:05:38 +02:00
Astro fdc6c38de6 enable_uart0(): add srcsel 2019-05-07 00:01:43 +02:00
Astro 55957eea09 regs macros 2019-05-06 23:56:53 +02:00
Astro 9b414e2408 PoC: boot, uart output in qemu 2019-05-05 14:56:23 +02:00