forked from M-Labs/zynq-rs
zynq::flash: refactor
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45cc271735
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41
src/zynq/flash/bytes.rs
Normal file
41
src/zynq/flash/bytes.rs
Normal file
@ -0,0 +1,41 @@
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pub trait BytesTransferExt: Sized {
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// Turn u32 into u8
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fn bytes_transfer(self) -> BytesTransfer<Self>
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where
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Self: Iterator<Item = u32>;
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}
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impl<I: Iterator<Item = u32>> BytesTransferExt for I {
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// Turn u32 into u8
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fn bytes_transfer(self) -> BytesTransfer<Self> {
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BytesTransfer {
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iter: self,
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shift: 32,
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word: 0,
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}
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}
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}
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pub struct BytesTransfer<I: Iterator<Item = u32> + Sized> {
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iter: I,
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shift: u8,
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word: u32,
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}
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impl<I: Iterator<Item = u32> + Sized> Iterator for BytesTransfer<I> {
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type Item = u8;
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fn next(&mut self) -> Option<u8> {
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if self.shift < 24 {
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self.shift += 8;
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Some((self.word >> self.shift) as u8)
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} else {
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self.shift = 0;
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self.iter.next()
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.map(|word| {
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self.word = word;
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word as u8
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})
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}
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}
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}
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@ -1,37 +0,0 @@
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use super::Transfer;
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pub trait Instruction {
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type Args: Iterator<Item = u32>;
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type Result: for<'r, 't> From<&'t mut Transfer<'r, Self::Args>>;
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fn inst_code() -> u8;
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fn args(&self) -> Self::Args;
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}
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pub struct ReadId;
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impl Instruction for ReadId {
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type Result = u32; // TODO: u8;
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type Args = core::iter::Empty<u32>;
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fn inst_code() -> u8 {
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0x9f
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}
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fn args(&self) -> Self::Args {
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core::iter::empty()
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}
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}
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/// Read configuration register
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pub struct RdCr;
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impl Instruction for RdCr {
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type Result = u8;
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type Args = core::iter::Empty<u32>;
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fn inst_code() -> u8 {
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0x35
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}
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fn args(&self) -> Self::Args {
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core::iter::empty()
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}
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}
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@ -6,7 +6,8 @@ use super::slcr;
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use super::clocks::CpuClocks;
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mod regs;
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mod instr;
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mod bytes;
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pub use bytes::{BytesTransferExt, BytesTransfer};
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const FLASH_BAUD_RATE: u32 = 50_000_000;
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const SINGLE_CAPACITY: u32 = 16 * 1024 * 1024;
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@ -312,136 +313,89 @@ impl Flash<Manual> {
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}
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pub fn rdcr(&mut self) -> u8 {
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self.transfer(instr::RdCr)
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self.transfer(0x35, core::iter::empty())
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.bytes_transfer().skip(1)
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.next().unwrap() as u8
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}
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pub fn transfer<I: instr::Instruction>(&mut self, input: I) -> I::Result {
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let mut t = Transfer::new(&mut self.regs, I::inst_code(), input.args());
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(&mut t).into()
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pub fn rdid(&mut self) -> core::iter::Skip<BytesTransfer<Transfer<core::iter::Empty<u32>>>> {
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self.transfer(0x9f, core::iter::empty())
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.bytes_transfer().skip(1)
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}
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pub fn read(&mut self, offset: u32, dest: &mut [u8]) {
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// Quad Read
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let instr = 0xEB;
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unsafe {
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self.regs.txd0.write(
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instr |
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(offset << 8)
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);
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}
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let mut n = 0;
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while !self.regs.intr_status.read().tx_fifo_full() {
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unsafe {
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self.regs.txd0.write(0);
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}
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n += 1;
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}
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self.regs.config.modify(|_, w| w
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.pcs(false)
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.man_start_com(true)
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);
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let mut offset = 0;
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while offset < dest.len() {
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while !self.regs.intr_status.read().rx_fifo_not_empty() {}
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// TODO: drops data?
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let rx = self.regs.rx_data.read();
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if offset < dest.len() {
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dest[offset] = rx as u8;
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}
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offset += 1;
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if offset < dest.len() {
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dest[offset] = (rx >> 8) as u8;
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}
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offset += 1;
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if offset < dest.len() {
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dest[offset] = (rx >> 16) as u8;
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}
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offset += 1;
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if offset < dest.len() {
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dest[offset] = (rx << 24) as u8;
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}
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offset += 1;
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// Output dummy byte to generate clock for further RX
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unsafe {
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self.regs.txd0.write(0);
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}
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}
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self.regs.config.modify(|_, w| w
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.pcs(true)
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.man_start_com(false)
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);
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}
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}
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pub struct Transfer<'r, Args: Iterator<Item = u32>> {
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regs: &'r mut regs::RegisterBlock,
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args: Args,
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}
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impl<'r, Args: Iterator<Item = u32>> Transfer<'r, Args> {
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pub fn new(regs: &'r mut regs::RegisterBlock, inst_code: u8, mut args: Args) -> Self
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pub fn transfer<'s: 't, 't, Args>(&'s mut self, inst_code: u8, args: Args) -> Transfer<'t, Args>
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where
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Args: Iterator<Item = u32>,
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{
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unsafe {
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regs.txd1.write(inst_code.into());
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Transfer::new(self, inst_code, args)
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}
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pub fn read(&mut self, offset: u32, len: usize) -> core::iter::Take<core::iter::Skip<BytesTransfer<Transfer<core::option::IntoIter<u32>>>>> {
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// TODO:
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let args = Some(0u32);
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// Quad Read
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self.transfer(0xEB, args.into_iter())
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.bytes_transfer().skip(1).take(len)
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}
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}
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pub struct Transfer<'a, Args: Iterator<Item = u32>> {
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flash: &'a mut Flash<Manual>,
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args: Args,
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}
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impl<'a, Args: Iterator<Item = u32>> Transfer<'a, Args> {
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pub fn new(flash: &'a mut Flash<Manual>, inst_code: u8, mut args: Args) -> Self
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where
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Args: Iterator<Item = u32>,
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{
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while flash.regs.intr_status.read().rx_fifo_not_empty() {
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flash.regs.rx_data.read();
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}
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while !regs.intr_status.read().tx_fifo_full() {
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unsafe {
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flash.regs.txd1.write(inst_code.into());
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}
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while !flash.regs.intr_status.read().tx_fifo_full() {
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let arg = args.next().unwrap_or(0);
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unsafe {
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regs.txd0.write(arg);
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flash.regs.txd0.write(arg);
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}
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}
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regs.config.modify(|_, w| w
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flash.regs.config.modify(|_, w| w
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.pcs(false)
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.man_start_com(true)
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);
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Transfer { regs, args }
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}
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pub fn recv(&mut self) -> u32 {
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while !self.regs.intr_status.read().rx_fifo_not_empty() {}
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let rx = self.regs.rx_data.read();
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let arg = self.args.next().unwrap_or(0);
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unsafe {
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self.regs.txd0.write(arg);
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Transfer {
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flash,
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args,
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}
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rx
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}
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}
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impl<'r, Args: Iterator<Item = u32>> Drop for Transfer<'r, Args> {
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impl<'a, Args: Iterator<Item = u32>> Drop for Transfer<'a, Args> {
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fn drop(&mut self) {
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self.regs.config.modify(|_, w| w
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.pcs(true)
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.man_start_com(false)
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self.flash.regs.config.modify(|_, w| w
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.pcs(false)
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.man_start_com(true)
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);
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}
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}
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impl<'a, Args: Iterator<Item = u32>> Iterator for Transfer<'a, Args> {
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type Item = u32;
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impl<'t, Args: Iterator<Item = u32>> From<&'t mut Transfer<'_, Args>> for u32 {
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fn from(t: &mut Transfer<'_, Args>) -> u32 {
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t.recv()
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}
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}
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impl<Args: Iterator<Item = u32>> From<&mut Transfer<'_, Args>> for u8 {
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fn from(t: &mut Transfer<'_, Args>) -> u8 {
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u32::from(t) as u8
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}
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}
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impl<Args: Iterator<Item = u32>> From<&mut Transfer<'_, Args>> for u16 {
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fn from(t: &mut Transfer<'_, Args>) -> u16 {
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u32::from(t) as u16
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fn next<'s>(&'s mut self) -> Option<u32> {
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while !self.flash.regs.intr_status.read().rx_fifo_not_empty() {}
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let rx = self.flash.regs.rx_data.read();
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let arg = self.args.next().unwrap_or(0);
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unsafe {
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self.flash.regs.txd0.write(arg);
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}
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Some(rx)
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}
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}
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