forked from M-Labs/zynq-rs
zynq::flash: fix + refactor
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cfaa1213e2
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45cc271735
37
src/zynq/flash/instr.rs
Normal file
37
src/zynq/flash/instr.rs
Normal file
@ -0,0 +1,37 @@
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use super::Transfer;
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pub trait Instruction {
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type Args: Iterator<Item = u32>;
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type Result: for<'r, 't> From<&'t mut Transfer<'r, Self::Args>>;
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fn inst_code() -> u8;
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fn args(&self) -> Self::Args;
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}
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pub struct ReadId;
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impl Instruction for ReadId {
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type Result = u32; // TODO: u8;
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type Args = core::iter::Empty<u32>;
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fn inst_code() -> u8 {
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0x9f
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}
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fn args(&self) -> Self::Args {
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core::iter::empty()
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}
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}
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/// Read configuration register
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pub struct RdCr;
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impl Instruction for RdCr {
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type Result = u8;
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type Args = core::iter::Empty<u32>;
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fn inst_code() -> u8 {
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0x35
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}
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fn args(&self) -> Self::Args {
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core::iter::empty()
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}
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}
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@ -5,7 +5,8 @@ use crate::regs::{RegisterR, RegisterW, RegisterRW};
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use super::slcr;
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use super::clocks::CpuClocks;
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pub mod regs;
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mod regs;
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mod instr;
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const FLASH_BAUD_RATE: u32 = 50_000_000;
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const SINGLE_CAPACITY: u32 = 16 * 1024 * 1024;
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@ -28,6 +29,44 @@ impl<MODE> Flash<MODE> {
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_mode: PhantomData,
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}
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}
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fn disable_interrupts(&mut self) {
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self.regs.intr_dis.write(
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regs::IntrDis::zeroed()
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.rx_overflow(true)
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.tx_fifo_not_full(true)
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.tx_fifo_full(true)
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.rx_fifo_not_empty(true)
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.rx_fifo_full(true)
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.tx_fifo_underflow(true)
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);
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}
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fn enable_interrupts(&mut self) {
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self.regs.intr_en.write(
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regs::IntrEn::zeroed()
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.rx_overflow(true)
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.tx_fifo_not_full(true)
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.tx_fifo_full(true)
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.rx_fifo_not_empty(true)
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.rx_fifo_full(true)
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.tx_fifo_underflow(true)
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);
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}
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fn clear_rx_fifo(&self) {
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while self.regs.intr_status.read().rx_fifo_not_empty() {
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let _ = self.regs.rx_data.read();
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}
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}
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fn clear_interrupt_status(&mut self) {
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self.regs.intr_status.write(
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regs::IntrStatus::zeroed()
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.rx_overflow(true)
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.tx_fifo_underflow(true)
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);
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}
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}
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impl Flash<()> {
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@ -160,8 +199,16 @@ impl Flash<()> {
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}
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fn configure(&mut self, divider: u32) {
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// Disable
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self.regs.enable.write(
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regs::Enable::zeroed()
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);
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self.disable_interrupts();
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self.regs.lqspi_cfg.write(
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regs::LqspiCfg::zeroed()
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);
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self.clear_rx_fifo();
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self.clear_interrupt_status();
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// for a baud_rate_div=1 LPBK_DLY_ADJ would be required
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let mut baud_rate_div = 2u32;
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@ -173,6 +220,7 @@ impl Flash<()> {
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.baud_rate_div(baud_rate_div as u8)
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.mode_sel(true)
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.leg_flsh(true)
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.holdb_dr(true)
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// 32 bits TX FIFO width
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.fifo_width(0b11)
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);
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@ -184,30 +232,13 @@ impl Flash<()> {
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}
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}
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fn disable_interrupts(&mut self) {
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self.regs.intr_dis.write(
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regs::IntrDis::zeroed()
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.rx_overflow(true)
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.tx_fifo_not_full(true)
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.tx_fifo_full(true)
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.rx_fifo_not_empty(true)
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.rx_fifo_full(true)
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.tx_fifo_underflow(true)
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);
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}
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fn clear_rx_fifo(&self) {
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while self.regs.intr_status.read().rx_fifo_not_empty() {
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let _ = self.regs.rx_data.read();
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}
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}
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pub fn linear_addressing_mode(self) -> Flash<LinearAddressing> {
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// Set manual start enable to auto mode.
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// Assert the chip select.
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self.regs.config.modify(|_, w| w
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.man_start_en(false)
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.pcs(false)
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.manual_cs(false)
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);
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self.regs.lqspi_cfg.write(regs::LqspiCfg::zeroed()
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@ -218,11 +249,15 @@ impl Flash<()> {
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.mode_en(true)
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// 2 devices
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.two_mem(true)
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.u_page(false)
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// Linear Addressing Mode
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.lq_mode(true)
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);
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self.regs.enable.modify(|_, w| w.spi_en(true));
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self.regs.enable.write(
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regs::Enable::zeroed()
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.spi_en(true)
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);
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self.transition()
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}
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@ -240,13 +275,14 @@ impl Flash<()> {
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// 2 devices
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.two_mem(true)
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.u_page(chip_index != 0)
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// Manual I/O mode
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.lq_mode(false)
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);
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self.regs.config.modify(|_, w| w
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.pcs(false)
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self.regs.enable.write(
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regs::Enable::zeroed()
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.spi_en(true)
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);
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self.regs.enable.modify(|_, w| w.spi_en(true));
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self.transition()
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}
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}
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@ -272,17 +308,21 @@ impl Flash<LinearAddressing> {
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impl Flash<Manual> {
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pub fn stop(self) -> Flash<()> {
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self.regs.enable.modify(|_, w| w.spi_en(false));
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// De-assert chip select.
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self.regs.config.modify(|_, w| w.pcs(true));
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self.transition()
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}
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pub fn rdcr(&mut self) -> u8 {
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self.transfer(instr::RdCr)
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}
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pub fn transfer<I: instr::Instruction>(&mut self, input: I) -> I::Result {
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let mut t = Transfer::new(&mut self.regs, I::inst_code(), input.args());
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(&mut t).into()
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}
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pub fn read(&mut self, offset: u32, dest: &mut [u8]) {
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self.regs.config.modify(|_, w| w.man_start_com(true));
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// Quad I/O Read
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// Quad Read
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let instr = 0xEB;
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unsafe {
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self.regs.txd0.write(
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@ -290,29 +330,118 @@ impl Flash<Manual> {
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(offset << 8)
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);
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}
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while self.regs.intr_status.read().tx_fifo_not_full() {
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let mut n = 0;
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while !self.regs.intr_status.read().tx_fifo_full() {
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unsafe {
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self.regs.txd0.write(0);
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}
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let rx = self.regs.rx_data.read();
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n += 1;
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}
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for d in dest {
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self.regs.config.modify(|_, w| w
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.pcs(false)
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.man_start_com(true)
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);
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let mut offset = 0;
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while offset < dest.len() {
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while !self.regs.intr_status.read().rx_fifo_not_empty() {}
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// TODO: drops data?
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let rx = self.regs.rx_data.read();
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*d = rx as u8;
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if offset < dest.len() {
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dest[offset] = rx as u8;
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}
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offset += 1;
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if offset < dest.len() {
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dest[offset] = (rx >> 8) as u8;
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}
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offset += 1;
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if offset < dest.len() {
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dest[offset] = (rx >> 16) as u8;
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}
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offset += 1;
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if offset < dest.len() {
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dest[offset] = (rx << 24) as u8;
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}
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offset += 1;
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// Output dummy byte to generate clock for further RX
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unsafe {
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self.regs.txd1.write(0);
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self.regs.txd0.write(0);
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}
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}
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}
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fn wait_tx_not_full(&self) {
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while self.regs.intr_status.read().tx_fifo_full() {}
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self.regs.config.modify(|_, w| w
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.pcs(true)
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.man_start_com(false)
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);
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}
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}
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pub struct Transfer<'r, Args: Iterator<Item = u32>> {
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regs: &'r mut regs::RegisterBlock,
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args: Args,
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}
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impl<'r, Args: Iterator<Item = u32>> Transfer<'r, Args> {
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pub fn new(regs: &'r mut regs::RegisterBlock, inst_code: u8, mut args: Args) -> Self
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where
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Args: Iterator<Item = u32>,
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{
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unsafe {
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regs.txd1.write(inst_code.into());
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}
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while !regs.intr_status.read().tx_fifo_full() {
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let arg = args.next().unwrap_or(0);
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unsafe {
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regs.txd0.write(arg);
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}
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}
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regs.config.modify(|_, w| w
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.pcs(false)
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.man_start_com(true)
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);
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Transfer { regs, args }
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}
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pub fn recv(&mut self) -> u32 {
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while !self.regs.intr_status.read().rx_fifo_not_empty() {}
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let rx = self.regs.rx_data.read();
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let arg = self.args.next().unwrap_or(0);
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unsafe {
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self.regs.txd0.write(arg);
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}
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rx
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}
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}
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impl<'r, Args: Iterator<Item = u32>> Drop for Transfer<'r, Args> {
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fn drop(&mut self) {
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self.regs.config.modify(|_, w| w
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.pcs(true)
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.man_start_com(false)
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);
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}
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}
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impl<'t, Args: Iterator<Item = u32>> From<&'t mut Transfer<'_, Args>> for u32 {
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fn from(t: &mut Transfer<'_, Args>) -> u32 {
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t.recv()
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}
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}
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impl<Args: Iterator<Item = u32>> From<&mut Transfer<'_, Args>> for u8 {
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fn from(t: &mut Transfer<'_, Args>) -> u8 {
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u32::from(t) as u8
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}
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}
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impl<Args: Iterator<Item = u32>> From<&mut Transfer<'_, Args>> for u16 {
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fn from(t: &mut Transfer<'_, Args>) -> u16 {
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u32::from(t) as u16
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}
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}
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