Commit Graph

68 Commits

Author SHA1 Message Date
Vadim Kaushan 698cb306ea
Enable gcc caching 2019-03-17 17:24:07 +03:00
Vadim Kaushan 87453e6b0a
Change PATH in CI script 2019-03-17 16:52:15 +03:00
Vadim Kaushan a8040bd24b
Check blobs in separate target 2019-03-17 16:45:28 +03:00
Vadim Kaushan 9352831150
Simplify CI scripts 2019-03-17 16:30:23 +03:00
Vadim Kaushan 41b4c1c1e6
Remove useless 'set' commands 2019-03-17 16:28:53 +03:00
Vadim Kaushan 662dcb67d2
Update Travis build matrix 2019-03-17 16:27:41 +03:00
bors[bot] 2450868523 Merge #21
21: Add 64-bit targets, reads for composite CSRs, bump version r=dvc94ch a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>
2019-03-01 15:40:36 +00:00
Vadim Kaushan a091d236dd Bump version 2019-03-01 17:48:59 +03:00
Vadim Kaushan 925c496949 Read composite CSRs as one 64-bit value 2019-03-01 17:46:35 +03:00
Vadim Kaushan b665adeb95 Refactoring: use get_bit() instead of shifts 2019-03-01 17:10:45 +03:00
Vadim Kaushan ab15a6a8c7 CI: check new targets 2019-03-01 17:02:13 +03:00
Vadim Kaushan 427c3b9035 Generate binaries for 64-bit targets 2019-03-01 17:00:36 +03:00
bors[bot] 70bdf2f2f7 Merge #20
20: move doc comments inside macro invocations r=Disasm a=euclio

[rust-lang/rust#57882](https://github.com/rust-lang/rust/pull/57882) is modifying the `unused_doc_comments` lint to fire on mistakenly documented macro expansions. Note that these doc comments are not currently used, since they are eliminated when the macro is expanded. A crater run detected that this crate will break due to this change, likely because of the use of `deny(unused_doc_comments)` or `deny(warnings)`.

While this kind of breakage is allowed under Rust's stability guarantees, I am opening PRs to affected crates to reduce the impact.

This PR protects your crate from future breakage by moving the offending doc comments inside the macro invocations.

Co-authored-by: Andy Russell <arussell123@gmail.com>
2019-02-19 20:31:01 +00:00
Andy Russell 8cbb3878e5
move doc comments inside macro invocations 2019-02-19 15:19:02 -05:00
bors[bot] c99d70bf02 Merge #19
19: Add team e-mail to authors r=dvc94ch a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>
2019-02-07 16:55:23 +00:00
Vadim Kaushan e2ed39decd Leave just team e-mail in authors 2019-02-07 19:53:22 +03:00
Vadim Kaushan 8d6b2fe111 Add team e-mail to authors 2019-02-06 22:20:15 +03:00
bors[bot] 1ee535e94f Merge #18
18: remove the unused 'const-fn' feature r=Disasm a=japaric

note that is technically a breaking change

Co-authored-by: Jorge Aparicio <jorge@japaric.io>
2019-02-06 16:03:42 +00:00
Jorge Aparicio 01cfa71fd0 remove the unused 'const-fn' feature 2019-02-06 16:48:23 +01:00
bors[bot] 4e3517aaec Merge #17
17: Update docs and bump version r=dvc94ch a=Disasm

cc @rust-embedded/riscv

Co-authored-by: Vadim Kaushan <admin@disasm.info>
2019-01-24 14:37:18 +00:00
Vadim Kaushan 6c82b0ae4c Bump version 2019-01-24 17:20:50 +03:00
Vadim Kaushan 16fdb16730 Update docs 2019-01-24 17:20:23 +03:00
Vadim Kaushan ac1cba597a Fix RISC-V name
https://riscv.org/risc-v-trademark-usage/
2019-01-24 17:19:32 +03:00
bors[bot] d67f4acc3b Merge #16
16: Build on stable r=dvc94ch a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>
2019-01-22 22:36:46 +00:00
Vadim Kaushan 7e2103e566 Check build on stable 2019-01-23 01:29:54 +03:00
Vadim Kaushan 02c9295587 Check binary blobs during CI 2019-01-23 01:29:54 +03:00
Vadim Kaushan a51143d366 Implement asm functions 2019-01-23 01:29:54 +03:00
Vadim Kaushan 061579f97e Call external functions when inline-asm is not set 2019-01-23 01:29:54 +03:00
Vadim Kaushan 41378757c0 Do not require const-fn and asm features 2019-01-23 01:29:54 +03:00
Vadim Kaushan 3652547073 Simplify #[cfg()] predicate expressions 2019-01-23 01:29:54 +03:00
bors[bot] 86ac78b4aa Merge #15
15: Refactoring: use new macros for M-mode CSRs r=dvc94ch a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>
2019-01-22 21:58:06 +00:00
Vadim Kaushan 52ad774fc1 Remove useless cfg_attr 2018-12-21 23:01:25 +01:00
Vadim Kaushan 921aa2bbec Refactoring: use new macros for M-mode CSRs 2018-12-21 22:49:23 +01:00
bors[bot] 8bffbd7291 Merge #12 #14
12: Add some S-Mode CSRs r=dvc94ch a=wangrunji0408

Add these S-Mode CSRs:
- `sstatus`
- `stvec`
- `sie`
- `sip`
- `scause`
- `stval`
- `sscratch`
- `sepc`
- `satp`

as well as:
- `time`
- `timeh`

and S-Mode instructions:
- `sfence.vma`

Most of the code have been tested in the [RustOS](https://github.com/wangrunji0408/RustOS) project.

14: Remove ecall and *ret instructions from riscv::asm r=dvc94ch a=Disasm

* *ret instructions should not be used directly in Rust code, they should be used in handlers, written in asm ([example](273f0d4f70/src/lib.rs (L294-L340))).
* ecall instruction should be wrapped into something like syscall(), which should be declared in another platform-specific crate.

Co-authored-by: WangRunji <wangrunji0408@163.com>
Co-authored-by: Vadim Kaushan <admin@disasm.info>
2018-12-18 22:25:29 +00:00
bors[bot] ca737e7a48 Merge #13
13: Replace no-op with unimplemented!() r=dvc94ch a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>
2018-12-18 22:22:42 +00:00
Vadim Kaushan b790a0e92a Replace no-op with unimplemented!() 2018-12-19 00:01:36 +03:00
Vadim Kaushan 9550fe0687 Remove ecall and *ret instructions from riscv::asm 2018-12-18 23:58:50 +03:00
WangRunji 8776d30d3b add S-Mode registers
- use macros to simplify CSR ops
- use crate 'bit_field' to make bits operation clear
2018-11-09 22:42:46 +08:00
WangRunji 9dc7b40fdd impl sfence_vma & sfence_vma_all 2018-11-09 22:27:19 +08:00
bors[bot] 4e16dd85ed Merge #10
10: these raw instructions are unsafe r=dvc94ch a=strake

`wfi` is safe, but the rest are not. Let's make them all unsafe until we have a better idea — the return types are wrong anyhow.


Co-authored-by: M Farkas-Dyck <strake888@gmail.com>
2018-08-19 17:02:05 +00:00
bors[bot] 591b7df808 Merge #9
9: use `NonZeroUsize` where appropriate r=dvc94ch a=strake



Co-authored-by: M Farkas-Dyck <strake888@gmail.com>
2018-08-19 11:12:24 +00:00
bors[bot] 489b88f66b Merge #8
8: mepc is word-size r=dvc94ch a=strake



Co-authored-by: M Farkas-Dyck <strake888@gmail.com>
2018-08-19 08:49:02 +00:00
M Farkas-Dyck 8e0faa9182 these raw instructions are unsafe 2018-08-18 10:26:59 -08:00
M Farkas-Dyck 5a88960ee0 use `NonZeroUsize` where appropriate 2018-08-18 10:15:10 -08:00
M Farkas-Dyck ecc69bda00 mepc is word-size 2018-08-18 10:10:08 -08:00
David Craven 8d530616c9
Build master branch too. 2018-08-12 09:12:57 +02:00
David Craven be2a15f34e Bump version and update url. 2018-08-12 08:59:12 +02:00
David Craven b03aae8850 Update README. 2018-08-12 08:59:12 +02:00
David Craven 5e55720ad8 Update bare-metal. 2018-08-12 08:59:12 +02:00
David Craven 34b2ba33cd Add inline-asm feature. 2018-08-12 08:59:12 +02:00