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119 Commits

Author SHA1 Message Date
Sean Cross 28ded4136a vexriscv: clone from riscv crate 
Base the vexriscv crate on the riscv crate, but add vexriscv-specific
instructions.

Signed-off-by: Sean Cross <sean@xobs.io>
 2019-12-28 18:12:31 +08:00
bors[bot] 0259333c75
Merge #34 
34: mip, satp: Allow writing to these privileged registers r=laanwj a=archshift

Per the RISC-V privileged ISA, these registers should be writable.

Co-authored-by: Gui Andrade <gh@archshift.com>
 2019-10-10 07:32:26 +00:00
Gui Andrade 7a9aa062a0 Allow writing directly to satp register 2019-10-08 18:10:38 -07:00
Gui Andrade 95c52341c4 mip: Add set/clear functions for bits 2019-10-08 17:57:29 -07:00
bors[bot] 0eda3c511c
Merge #32 
32: add user trap setup and handling registers r=almindor a=almindor

Adds CSR handlers for user trap setup and handling registers.

Also unifies common shared types.

NOTE: untested, will test on real device ASAP

Co-authored-by: Ales Katona <almindor@gmail.com>
 2019-09-13 21:15:02 +00:00
Ales Katona 73f45e3dbf
Merge branch 'master' into ustatus 2019-09-13 11:21:44 -06:00
bors[bot] 9d68612325
Merge #33 
33: Do not use bare-metal v0.2.5 r=almindor a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>
 2019-09-13 01:06:16 +00:00
Vadim Kaushan b834ae45a5
Do not use bare-metal v0.2.5 (changes MSRV) 2019-09-05 19:53:02 +03:00
Ales Katona 8840aee369
ucause only as readable bits 2019-08-31 17:32:43 -06:00
Ales Katona e1232ed680
clean up formatting 2019-08-31 16:12:39 -06:00
Ales Katona cdf6a33665
remove XS and FS from ustatus 2019-08-31 16:10:56 -06:00
Ales Katona 13831f7a80
revert scause specific trap/exceptions 2019-08-31 16:09:47 -06:00
Ales Katona f443bcf698
remove invalid comment 2019-08-28 09:26:02 -06:00
Ales Katona 30555e4d79
fix typos in asm calls 2019-08-27 09:47:57 -06:00
Ales Katona 49446ad869
fix ustatus doc typos 2019-08-27 09:46:14 -06:00
Ales Katona 2180ef44d5
add user trap setup and handling registers 2019-08-27 09:40:47 -06:00
bors[bot] 4094a32f43 Merge #30 
30: add riscv32i target r=Disasm a=sbourdeauducq

This adds support for the simplest RISC-V processor possible, which is useful e.g. for experimenting with  FPGA softcore implementations.

Co-authored-by: Sebastien Bourdeauducq <sb@m-labs.hk>
 2019-07-27 12:59:37 +00:00
Sebastien Bourdeauducq b53e0a5cd2 add riscv32i target 2019-07-26 00:13:38 +08:00
bors[bot] 7f1e4a56cf Merge #31 
31: Add more CSRs r=laanwj a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>
 2019-07-23 17:41:40 +00:00
Vadim Kaushan d3dc245ce4
Bump version (0.5.4) 2019-07-03 01:37:34 +03:00
Vadim Kaushan 31f4127702
Add PMP CSRs 2019-06-26 11:25:45 +03:00
Vadim Kaushan f37ab221c8
Implement hpmcounter*[h], mhpmcounter*[h], mhpmevent* CSRs 2019-06-26 00:51:37 +03:00
Vadim Kaushan 298a8b6f6e
Provide write() for mepc 2019-06-25 23:48:47 +03:00
Vadim Kaushan 7a8d3d1f6c
Implement mscratch and mtval registers 2019-06-25 23:48:27 +03:00
Vadim Kaushan 00367d4fd2
Add sections to the registers module 2019-06-25 23:34:47 +03:00
Vadim Kaushan 370a654d2c
Regenerate binaries 2019-06-25 23:34:20 +03:00
Vadim Kaushan a659a0cc39
Declare all the CSR registers in asm.S 2019-06-25 23:33:40 +03:00
Vadim Kaushan ac2ac6756b
Derive useful traits for enums 2019-06-25 23:32:51 +03:00
bors[bot] 5a1ab837b4 Merge #28 
28: Add marchid, mhartid and mimpid registers r=laanwj a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>
 2019-06-25 19:40:12 +00:00
Vadim Kaushan 2965734b7b
Bump version (0.5.3) 2019-04-29 10:45:19 +02:00
Vadim Kaushan 2ef11206bd
Regenerate binaries 2019-04-29 10:44:45 +02:00
Vadim Kaushan cf9008492a
Add marchid, mhartid and mimpid registers 2019-04-29 10:43:51 +02:00
bors[bot] 1e514648fd Merge #26 
26: Fix Misa::has_extension() r=dvc94ch a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>
 2019-04-01 19:06:47 +00:00
Vadim Kaushan c3ff23989e
Bump version (0.5.2) 2019-04-01 19:59:10 +03:00
Vadim Kaushan ca797a35d8
Fix Misa::has_extension() 2019-04-01 19:58:40 +03:00
bors[bot] 33070435a0 Merge #25 
25: Rename RISCV to RISC-V in documentation r=Disasm a=medusacle

More common name for the CPU architecture 😄  Also update the copyright year.

Probably, if this is merged, you'd want to update the project description as well.

Co-authored-by: mara <vmedea@protonmail.com>
 2019-03-28 21:20:43 +00:00
bors[bot] 6425cab701 Merge #24 
24: Add FS and XS fields, fix incorrect field setting, bump version r=dvc94ch a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>
 2019-03-28 20:47:36 +00:00
mara c1a3fe2dd9 Rename RISCV to RISC-V 2019-03-28 18:31:57 +01:00
Vadim Kaushan 6bfccad567
Bump version (0.5.1) 2019-03-28 19:06:40 +03:00
Vadim Kaushan 7112ef8af2
Regenerate blobs 2019-03-28 18:57:28 +03:00
Vadim Kaushan 5baba0cb32
Add write function for sstatus register 2019-03-28 18:56:49 +03:00
Vadim Kaushan 9bb3b5803c
Refactoring: use set_bits() in set_fs function 2019-03-28 17:59:07 +03:00
Vadim Kaushan 5ef90e3189
Fix set_spp and set_mpp functions 2019-03-28 17:57:40 +03:00
Vadim Kaushan 6a2bdbf38d
Refactoring 2019-03-18 18:25:16 +03:00
Vadim Kaushan 4fb81f4860
Add FS and XS fields of mstatus 2019-03-18 18:14:00 +03:00
bors[bot] 32eba6c1ea Merge #23 
23: Add fcsr register r=dvc94ch a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>
 2019-03-17 18:47:24 +00:00
Vadim Kaushan 8222812d8d
Regenerate blobs 2019-03-17 19:06:48 +03:00
Vadim Kaushan 4ad2150a24
Add fcsr register 2019-03-17 19:06:29 +03:00
bors[bot] 037e8bdcf4 Merge #22 
22: Update CI, add MSRV policy r=dvc94ch a=Disasm



Co-authored-by: Vadim Kaushan <admin@disasm.info>
 2019-03-17 14:47:55 +00:00
Vadim Kaushan 7d4919a67c
Add MSRV policy 2019-03-17 17:29:48 +03:00