cxp GW: add write_pointer csr

pipeline GW: cleanup

src/gateware/cxp.py

@@ -0,0 +1,384 @@
+from migen import *
+from migen.genlib.cdc import MultiReg, PulseSynchronizer
+from misoc.interconnect.csr import *
+
+from cxp_downconn import CXP_DownConn_PHYS
+from cxp_upconn import CXP_UpConn_PHYS
+from cxp_pipeline import *
+
+
+class CXP_PHYS(Module, AutoCSR):
+    def __init__(self, refclk, upconn_pads, downconn_pads, sys_clk_freq, debug_sma, pmod_pads):
+        assert len(upconn_pads) == len(downconn_pads)
+        self.submodules.upconn = CXP_UpConn_PHYS(upconn_pads, sys_clk_freq, debug_sma, pmod_pads)
+        self.submodules.downconn = CXP_DownConn_PHYS(refclk, downconn_pads, sys_clk_freq, debug_sma, pmod_pads)
+
+@FullMemoryWE()
+class CXP_Interface(Module, AutoCSR):
+    def __init__(self, upconn_phy, downconn_phy, debug_sma, pmod_pads):
+        # TODO: move all transceiver csr into a transceiver interface submodule
+        
+        self.submodules.upconn = UpConn_Interface(upconn_phy, debug_sma, pmod_pads)
+
+        self.submodules.downconn = DownConn_Interface(downconn_phy, debug_sma, pmod_pads)
+
+    def get_tx_port(self):
+        return self.upconn.command.mem.get_port(write_capable=True)
+
+    def get_rx_port(self):
+        return self.downconn.packet_decoder.mem.get_port(write_capable=False)
+
+    def get_loopback_tx_port(self):
+        return self.downconn.command.mem.get_port(write_capable=True)
+    
+    def get_mem_size(self):
+        return buffer_depth*word_dw
+
+class DownConn_Interface(Module, AutoCSR):
+    def __init__(self, phy, debug_sma, pmod_pads):
+        self.rx_start_init = CSRStorage()
+        self.rx_restart = CSR()
+        self.rx_ready = CSRStatus()
+
+        # # #
+
+        gtx = phy.gtx
+
+        # GTX Control
+        self.sync += [
+            gtx.rx_restart.eq(self.rx_restart.re),
+            gtx.rx_init.clk_path_ready.eq(self.rx_start_init.storage),
+            self.rx_ready.status.eq(gtx.rx_ready),
+        ]
+
+
+        # DEBUG: tx control
+        self.tx_start_init = CSRStorage()
+        self.tx_restart = CSR()
+        self.txenable = CSRStorage()
+        self.sync += [
+            gtx.txenable.eq(self.txenable.storage),
+            gtx.tx_restart.eq(self.tx_restart.re),
+            gtx.tx_init.clk_path_ready.eq(self.tx_start_init.storage),
+        ]
+
+        # DEBUG: loopback control
+        self.loopback_mode = CSRStorage(3)
+        self.comb += gtx.loopback_mode.eq(self.loopback_mode.storage) 
+
+        
+        # DEBUG: init status
+        self.txinit_phaligndone = CSRStatus()
+        self.rxinit_phaligndone = CSRStatus()
+        self.comb += [
+            self.txinit_phaligndone.status.eq(gtx.tx_init.Xxphaligndone),
+            self.rxinit_phaligndone.status.eq(gtx.rx_init.Xxphaligndone),
+        ]
+
+        # Connect all GTX connections' DRP
+        self.gtx_daddr = CSRStorage(9)
+        self.gtx_dread = CSR()
+        self.gtx_din_stb = CSR()
+        self.gtx_din = CSRStorage(16)
+
+        self.gtx_dout = CSRStatus(16)
+        self.gtx_dready = CSR()
+
+        self.comb += gtx.dclk.eq(ClockSignal("sys"))
+        self.sync += [
+            gtx.den.eq(0),
+            gtx.dwen.eq(0),
+            If(self.gtx_dread.re,
+                gtx.den.eq(1),
+                gtx.daddr.eq(self.gtx_daddr.storage),
+            ).Elif(self.gtx_din_stb.re,
+                gtx.den.eq(1),
+                gtx.dwen.eq(1),
+                gtx.daddr.eq(self.gtx_daddr.storage),
+                gtx.din.eq(self.gtx_din.storage),
+            ),
+            If(gtx.dready,
+               self.gtx_dready.w.eq(1),
+               self.gtx_dout.status.eq(gtx.dout),
+            ),
+            If(self.gtx_dready.re,
+               self.gtx_dready.w.eq(0),
+            ),
+        ]
+
+
+        # DEBUG: txusrclk PLL DRP
+        
+        self.txpll_reset = CSRStorage()
+        self.pll_daddr = CSRStorage(7)
+        self.pll_dclk = CSRStorage()
+        self.pll_den = CSRStorage()
+        self.pll_din = CSRStorage(16)
+        self.pll_dwen = CSRStorage()
+
+        self.txpll_locked = CSRStatus()
+        self.pll_dout = CSRStatus(16)
+        self.pll_dready = CSRStatus()
+
+        self.comb += [
+            gtx.txpll_reset.eq(self.txpll_reset.storage),
+            gtx.pll_daddr.eq(self.pll_daddr.storage),
+            gtx.pll_dclk.eq(self.pll_dclk.storage),
+            gtx.pll_den.eq(self.pll_den.storage),
+            gtx.pll_din.eq(self.pll_din.storage),
+            gtx.pll_dwen.eq(self.pll_dwen.storage),
+
+            self.txinit_phaligndone.status.eq(gtx.tx_init.Xxphaligndone),
+            self.rxinit_phaligndone.status.eq(gtx.rx_init.Xxphaligndone),
+            self.txpll_locked.status.eq(gtx.txpll_locked),
+            self.pll_dout.status.eq(gtx.pll_dout),
+            self.pll_dready.status.eq(gtx.pll_dready),
+        ]
+
+
+        # DEBUG: tx loopback fifo control
+        self.tx_stb = CSRStorage()
+        self.sync += phy.tx_stb_sys.eq(self.tx_stb.storage) 
+   
+
+        # DEBUG: Transmission Pipeline
+        # 
+        # test pak ----+
+        # from gw      |   32                                            32
+        #              |---/---> mux -----> packet -----> trigger ack ---/---> PHY
+        #              |                    wrapper       inserter
+        # data pak ----+
+        # from fw
+        
+
+        # DEBUG: TX pipeline
+        self.submodules.command = command = TX_Command_Packet()
+        self.submodules.testseq = testseq = TX_Test_Packet()
+        self.submodules.mux = mux = stream.Multiplexer(word_layout, 2)
+        self.submodules.pak_wrp = pak_wrp = Packet_Wrapper()
+        self.submodules.trig_ack = trig_ack = Trigger_ACK_Inserter()
+
+        self.ack = CSR()
+        self.mux_sel = CSRStorage()
+
+        self.sync += trig_ack.stb.eq(self.ack.re),
+        self.comb += [
+            command.source.connect(mux.sink0),
+            testseq.source.connect(mux.sink1),
+            mux.sel.eq(self.mux_sel.storage),
+        ]
+
+        tx_pipeline = [mux , pak_wrp, trig_ack, phy]
+        for s, d in zip(tx_pipeline, tx_pipeline[1:]):
+            self.comb += s.source.connect(d.sink)
+
+
+
+
+        # Receiver Pipeline WIP
+        # 
+        #        32                32
+        # PHY ---/---> CDC FIFO ---/---> trigger ack ------> packet  ------> debug buffer
+        #                                checker             decoder
+        #
+        cdr = ClockDomainsRenamer("cxp_gtx_rx")
+
+        # Priority level 1 packet - Trigger ack packet
+        self.submodules.trig_ack_checker = trig_ack_checker = cdr(CXP_Trig_Ack_Checker())
+        
+        self.submodules.trig_ack_ps = trig_ack_ps = PulseSynchronizer("cxp_gtx_rx", "sys")
+        self.comb += trig_ack_ps.i.eq(trig_ack_checker.ack)
+
+        self.trig_ack = Signal()
+        self.trig_clr = Signal()
+        # Error are latched
+        self.sync += [
+            If(trig_ack_ps.o,
+                self.trig_ack.eq(1),
+            ).Elif(self.trig_clr,
+                self.trig_ack.eq(0),
+            ),
+        ]
+
+        # Priority level 2 packet - data, test packet
+        self.submodules.packet_decoder = packet_decoder = cdr(CXP_Data_Packet_Decode())
+
+        self.new_rx_packet = CSR()
+        self.decoder_error = CSR()
+        self.test_error = CSR()
+
+        self.submodules.new_packet_ps = new_packet_ps = PulseSynchronizer("cxp_gtx_rx", "sys")
+        self.submodules.decode_err_ps = decode_err_ps = PulseSynchronizer("cxp_gtx_rx", "sys")
+        self.submodules.test_err_ps = test_err_ps = PulseSynchronizer("cxp_gtx_rx", "sys")
+        self.comb += [
+            new_packet_ps.i.eq(packet_decoder.new_packet),
+            decode_err_ps.i.eq(packet_decoder.decode_err),
+            test_err_ps.i.eq(packet_decoder.test_err),
+        ]
+        self.sync += [
+            If(new_packet_ps.o,
+                self.new_rx_packet.w.eq(1),
+            ).Elif(self.new_rx_packet.re,
+                self.new_rx_packet.w.eq(0),
+            ),
+            If(decode_err_ps.o,
+                self.decoder_error.w.eq(1),
+            ).Elif(self.decoder_error.re,
+                self.decoder_error.w.eq(0),
+            ),
+            If(test_err_ps.o,
+                self.test_error.w.eq(1),
+            ).Elif(self.test_error.re,
+                self.test_error.w.eq(0),
+            ),
+        ]
+
+
+        # Cicular buffer interface
+        self.packet_type = CSRStatus(8)
+        self.write_pointer = CSRStatus(bits_for(buffer_depth)) # for firmware to sync with buffer
+
+        self.specials += [
+            MultiReg(packet_decoder.packet_type, self.packet_type.status),
+            MultiReg(packet_decoder.write_ptr, self.write_pointer.status),
+        ]
+
+        # DEBUG: remove this cdc fifo
+        cdc_fifo = stream.AsyncFIFO(word_layout, 512)
+        self.submodules += ClockDomainsRenamer({"write": "cxp_gtx_rx", "read": "sys"})(cdc_fifo)
+        self.submodules.debug_out = debug_out = RX_Debug_Buffer()
+
+
+        rx_pipeline = [phy, trig_ack_checker, packet_decoder, cdc_fifo, debug_out]
+        for s, d in zip(rx_pipeline, rx_pipeline[1:]):
+            self.comb += s.source.connect(d.sink)
+        
+
+        # DEBUG: CSR
+        self.trigger_ack = CSR()
+        self.sync += [
+            self.trig_clr.eq(self.trigger_ack.re),
+            self.trigger_ack.w.eq(self.trig_ack),
+        ]
+
+        pak_start = Signal()
+        self.sync += [
+            pak_start.eq(packet_decoder.sink.data == 0xFBFBFBFB),
+        ]
+
+        self.specials += [
+            Instance("OBUF", i_I=phy.gtx.cd_cxp_gtx_rx.clk, o_O=debug_sma.p_tx),
+            # Instance("OBUF", i_I=, o_O=debug_sma.p_rx),
+            # # pmod 0-7 pin
+            Instance("OBUF", i_I=packet_decoder.test_err, o_O=pmod_pads[0]),
+            Instance("OBUF", i_I=pak_start, o_O=pmod_pads[1]),
+            # Instance("OBUF", i_I=fifo_in.source.ack, o_O=pmod_pads[2]),
+            # Instance("OBUF", i_I=gtx.comma_checker.aligner_en, o_O=pmod_pads[3]),
+            # Instance("OBUF", i_I=gtx.comma_checker.check_reset, o_O=pmod_pads[4]),
+            # Instance("OBUF", i_I=gtx.comma_checker.has_comma, o_O=pmod_pads[5]),
+            # Instance("OBUF", i_I=gtx.comma_checker.has_error, o_O=pmod_pads[6]),
+            # Instance("OBUF", i_I=gtx.comma_checker.ready_sys, o_O=pmod_pads[7]),
+        ]
+
+        
+class UpConn_Interface(Module, AutoCSR):
+    def __init__(self, phy, debug_sma, pmod_pads):
+        self.clk_reset = CSRStorage(reset=1)
+        self.bitrate2x_enable = CSRStorage()
+        self.tx_enable = CSRStorage()
+
+        # TODO: add busy condition
+        self.tx_busy = CSRStatus()
+
+        self.tx_testmode_en = CSRStorage()
+
+        # # #
+
+        self.sync += [
+            phy.bitrate2x_enable.eq(self.bitrate2x_enable.storage),
+            phy.tx_enable.eq(self.tx_enable.storage),
+            phy.clk_reset.eq(self.clk_reset.re),
+        ]
+
+
+        # Transmission Pipeline
+        # 
+        # test pak ----+
+        # from gw      |   32                                                             32           8
+        #              |---/---> mux -----> packet -----> idle word -----> trigger ack ---/--> conv ---/---> trigger -----> PHY
+        #              |                    wrapper       inserter         inserter                          inserter
+        # data pak ----+
+        # from fw
+        #
+        # Equivalent transmission priority:
+        # trigger > trigger ack > idle > test/data packet
+        # To maintain the trigger performance, idle word should not be inserted into trigger or trigger ack.
+        # 
+        # In low speed CoaXpress, the higher priority packet can be inserted in two types of boundary
+        # Insertion @ char boundary: Trigger packets
+        # Insertion @ word boundary: Trigger ack & IDLE packets
+        # The 32 bit part of the pipeline handles the word boundary insertion while the 8 bit part handles the char boundary insertion
+        
+
+
+        # Packet FIFOs with transmission priority
+        # 0: Trigger packet
+        self.submodules.trig = trig = TX_Trigger()
+        
+        # # DEBUG: INPUT
+        self.trig_stb = CSR()
+        self.trig_delay = CSRStorage(8) 
+        self.linktrigger = CSRStorage(2)
+
+        self.sync += [
+            trig.stb.eq(self.trig_stb.re),
+            trig.delay.eq(self.trig_delay.storage),
+            trig.linktrig_mode.eq(self.linktrigger.storage),
+        ]
+
+        
+        # 1: IO acknowledgment for trigger packet
+        self.submodules.trig_ack = trig_ack = Trigger_ACK_Inserter()
+
+        # DEBUG: INPUT
+        self.ack = CSR()
+        self.sync += trig_ack.stb.eq(self.ack.re),
+
+
+        # 2: All other packets (data & test packet)
+        # Control is not timing dependent, all the data packets are handled in firmware
+
+        self.submodules.command = command = TX_Command_Packet()
+        self.submodules.testseq = testseq = TX_Test_Packet()
+        self.submodules.mux = mux = stream.Multiplexer(word_layout, 2)
+
+        self.comb += [
+            command.source.connect(mux.sink0),
+            testseq.source.connect(mux.sink1),
+            mux.sel.eq(self.tx_testmode_en.storage),
+        ]
+
+        self.submodules.pak_wrp = pak_wrp = Packet_Wrapper()
+
+        # IDLE Word
+        self.submodules.idle = idle = Idle_Word_Inserter()
+
+        # Section 9.2.5.1 (CXP-001-2021)
+        # IDLE should be transmitter every 10000 words
+        cnt = Signal(max=10000)
+
+        self.sync += [
+            idle.stb.eq(0),
+            If((~idle.sink.stb) | (cnt == 9999),
+               idle.stb.eq(1),
+               cnt.eq(cnt.reset),
+            ).Else(
+               cnt.eq(cnt + 1),
+            ),
+        ]
+        
+        self.submodules.converter = converter = stream.StrideConverter(word_layout, char_layout)
+
+        tx_pipeline = [mux, pak_wrp, idle, trig_ack, converter, trig, phy]
+        for s, d in zip(tx_pipeline, tx_pipeline[1:]):
+            self.comb += s.source.connect(d.sink)

src/gateware/cxp_downconn.py

@@ -0,0 +1,709 @@
+from migen import *
+from migen.genlib.cdc import MultiReg
+from migen.genlib.resetsync import AsyncResetSynchronizer
+
+from misoc.cores.code_8b10b import Encoder, Decoder
+from misoc.interconnect.csr import *
+from misoc.interconnect import stream
+
+from artiq.gateware.drtio.transceiver.gtx_7series_init import *
+from cxp_pipeline import word_layout
+
+from functools import reduce
+from operator import add
+
+class CXP_DownConn_PHYS(Module, AutoCSR):
+    def __init__(self, refclk, pads, sys_clk_freq, debug_sma, pmod_pads):
+        self.qpll_reset = CSR()
+        self.qpll_locked = CSRStatus()
+
+        self.rx_phys = []
+        # # #
+
+        # For speed higher than 6.6Gbps, QPLL need to be used instead of CPLL
+        self.submodules.qpll = qpll = QPLL(refclk, sys_clk_freq)
+        self.sync += [
+            qpll.reset.eq(self.qpll_reset.re),
+            self.qpll_locked.status.eq(qpll.lock),
+        ]
+
+
+        for i, pad in enumerate(pads):
+            rx = Receiver(qpll, pad, sys_clk_freq, "single", "single", debug_sma, pmod_pads)
+            self.rx_phys.append(rx)
+            setattr(self.submodules, "rx"+str(i), rx)
+
+            # TODO: add extension gtx connections
+            # TODO: add connection interface
+
+        # TODO: Connect slave cxp_gtx_rx clock tgt
+        # checkout channel interfaces & drtio_gtx
+        # GTPTXPhaseAlignement for inspiration
+
+
+class Receiver(Module):
+    def __init__(self, qpll, pad, sys_clk_freq, tx_mode, rx_mode, debug_sma, pmod_pads):
+        self.submodules.gtx = gtx = GTX(qpll, pad, sys_clk_freq, tx_mode="single", rx_mode="single")
+       
+        self.source = stream.Endpoint(word_layout)
+
+        self.sync.cxp_gtx_rx += [
+            self.source.stb.eq(0),
+            If(gtx.rx_ready & self.source.ack & ~((gtx.decoders[0].d == 0xBC) & (gtx.decoders[0].k == 1)),
+                self.source.stb.eq(1),
+                self.source.data.eq(Cat(gtx.decoders[0].d, gtx.decoders[1].d, gtx.decoders[2].d, gtx.decoders[3].d)),
+                self.source.k.eq(Cat(gtx.decoders[0].k, gtx.decoders[1].k, gtx.decoders[2].k, gtx.decoders[3].k)),
+            )
+        ]
+
+        # DEBUG: tx fifos for loopback
+        # fw -> fifo (sys) -> cdc fifo -> gtx tx
+        
+        tx_fifo = stream.AsyncFIFO(word_layout, 512)
+        self.submodules += ClockDomainsRenamer({"write": "sys", "read": "cxp_gtx_tx"})(tx_fifo)
+        self.sink = tx_fifo.sink
+    
+        self.tx_stb_sys = Signal()
+        txstb = Signal()
+        self.specials += MultiReg(self.tx_stb_sys, txstb, odomain="cxp_gtx_tx")
+
+        word_count = Signal(max=100)
+
+        # JANK: fix the every 98th word got eaten
+        # cnt      97    98   99       0
+        # out fifo[97] IDLE IDLE fifo[99]
+        # ack       1     0    0       1
+        self.sync.cxp_gtx_tx += [
+            tx_fifo.source.ack.eq(0),
+
+            If(word_count == 99,
+                word_count.eq(word_count.reset),
+            ).Else(
+                If(tx_fifo.source.stb & txstb,
+                    If(word_count != 98, tx_fifo.source.ack.eq(1)),
+                    word_count.eq(word_count + 1),
+                )
+            )
+        ]
+
+        # NOTE: prevent the first word send twice due to stream stb delay 
+        self.comb += [
+            If((tx_fifo.source.stb & tx_fifo.source.ack & (word_count != 99)),
+                gtx.encoder.d[0].eq(tx_fifo.source.data[:8]),
+                gtx.encoder.d[1].eq(tx_fifo.source.data[8:16]),
+                gtx.encoder.d[2].eq(tx_fifo.source.data[16:24]),
+                gtx.encoder.d[3].eq(tx_fifo.source.data[24:]),
+                gtx.encoder.k[0].eq(tx_fifo.source.k[0]),
+                gtx.encoder.k[1].eq(tx_fifo.source.k[1]),
+                gtx.encoder.k[2].eq(tx_fifo.source.k[2]),
+                gtx.encoder.k[3].eq(tx_fifo.source.k[3]),
+            ).Else(
+                # NOTE: IDLE WORD
+                gtx.encoder.d[0].eq(0xBC),
+                gtx.encoder.k[0].eq(1),
+                gtx.encoder.d[1].eq(0x3C),
+                gtx.encoder.k[1].eq(1),
+                gtx.encoder.d[2].eq(0x3C),
+                gtx.encoder.k[2].eq(1),
+                gtx.encoder.d[3].eq(0xB5),
+                gtx.encoder.k[3].eq(0),
+            )
+        ]
+
+
+class QPLL(Module, AutoCSR):
+    def __init__(self, refclk, sys_clk_freq):
+        self.clk = Signal()
+        self.refclk = Signal()
+        self.lock = Signal()
+        self.reset = Signal()
+
+        self.daddr = CSRStorage(8)
+        self.dread = CSR()
+        self.din_stb = CSR()
+        self.din = CSRStorage(16)
+
+        self.dout = CSRStatus(16)
+        self.dready = CSR()
+
+        # # #
+
+        # VCO @ 10GHz, linerate = 1.25Gbps
+        # feedback divider = 80
+        qpll_fbdiv = 0b0100100000
+        qpll_fbdiv_ratio = 1
+        refclk_div = 1
+        self.Xxout_div = 8
+
+        # DEBUG: txuserclk
+        fbdiv_real = 80
+        self.tx_usrclk_freq = (sys_clk_freq*fbdiv_real/self.Xxout_div)/40
+        
+        dready = Signal()
+        self.specials += [
+            Instance("GTXE2_COMMON",
+                i_QPLLREFCLKSEL=0b001,
+                i_GTREFCLK0=refclk,         
+
+                i_QPLLPD=0,
+                i_QPLLRESET=self.reset,
+                i_QPLLLOCKEN=1,
+                o_QPLLLOCK=self.lock,
+                o_QPLLOUTCLK=self.clk,
+                o_QPLLOUTREFCLK=self.refclk,
+
+                # See UG476 (v1.12.1) Table 2-16
+                p_QPLL_FBDIV=qpll_fbdiv,
+                p_QPLL_FBDIV_RATIO=qpll_fbdiv_ratio,
+                p_QPLL_REFCLK_DIV=refclk_div,
+
+                # From 7 Series FPGAs Transceivers Wizard
+                p_BIAS_CFG=0x0000040000001000,
+                p_COMMON_CFG=0x00000000,
+                p_QPLL_CFG=0x0680181,
+                p_QPLL_CLKOUT_CFG=0b0000,
+                p_QPLL_COARSE_FREQ_OVRD=0b010000,
+                p_QPLL_COARSE_FREQ_OVRD_EN=0b0,
+                p_QPLL_CP=0b0000011111,
+                p_QPLL_CP_MONITOR_EN=0b0,
+                p_QPLL_DMONITOR_SEL=0b0,
+                p_QPLL_FBDIV_MONITOR_EN= 0b0,
+                p_QPLL_INIT_CFG=0x000006,
+                p_QPLL_LOCK_CFG=0x21E8,
+                p_QPLL_LPF=0b1111,
+             
+                # Reserved, values cannot be modified
+                i_BGBYPASSB=0b1,
+                i_BGMONITORENB=0b1,
+                i_BGPDB=0b1,
+                i_BGRCALOVRD=0b11111,
+                i_RCALENB=0b1,
+                i_QPLLRSVD1=0b0,
+                i_QPLLRSVD2=0b11111,
+
+                # Dynamic Reconfiguration Ports
+                i_DRPADDR=self.daddr.storage,
+                i_DRPCLK=ClockSignal("sys"),
+                i_DRPEN=(self.dread.re | self.din_stb.re),
+                i_DRPWE=self.din_stb.re,
+                i_DRPDI=self.din.storage,
+                o_DRPDO=self.dout.status,
+                o_DRPRDY=dready,
+            )
+        ]
+
+        self.sync += [
+            If(dready,
+               self.dready.w.eq(1),
+            ),
+            If(self.dready.re,
+               self.dready.w.eq(0),
+            ),
+        ]
+
+# Warning: Xilinx transceivers are LSB first, and comma needs to be flipped
+# compared to the usual 8b10b binary representation.
+class Comma_Checker(Module):
+    def __init__(self, comma, reset_period=10_000_000):
+        self.data = Signal(20)
+        self.comma_aligned = Signal()
+        self.comma_realigned = Signal()
+        self.comma_det = Signal()
+
+        self.aligner_en = Signal()
+        self.ready_sys = Signal()
+        self.restart_sys = Signal()
+
+        # # #
+
+
+        # periodically reset rx until rx is connected and receiving valid data
+        # as after connecting RXP/RXN, the whole RX need to be reset 
+        
+        reset_counter = Signal(reset=reset_period-1, max=reset_period)
+        self.sync += [
+            self.restart_sys.eq(0),
+            If(~self.ready_sys,
+                If(reset_counter == 0,
+                    reset_counter.eq(reset_counter.reset),
+                    self.restart_sys.eq(1),
+                ).Else(
+                    reset_counter.eq(reset_counter - 1),
+                )
+            )
+        ]
+
+
+        # Data and comma checker
+        # From UG476 (v1.12.1) p.228
+        # The built-in RXBYTEISALIGNED can be falsely asserted at linerate higher than 5Gbps
+        # The validity of data and comma needed to be checked externally
+
+        comma_n = ~comma & 0b1111111111
+
+        # DEBUG: remove after use
+        self.has_comma = Signal()
+        self.has_error = Signal()
+
+        comma_seen = Signal()
+        error_seen = Signal()
+        one_counts = Signal(max=11)
+
+        # From CXP-001-2021 section 9.2.5.1
+        # For high speed connection an IDLE word shall be transmitted at least once every 100 words
+        counter_period = 200
+
+        counter = Signal(reset=counter_period-1, max=counter_period)
+        check_reset = Signal()
+        check = Signal()
+
+        self.sync.cxp_gtx_rx += [
+            If(check_reset,
+                counter.eq(counter.reset),   
+                check.eq(0),
+            ).Elif(counter == 0,
+                check.eq(1),
+            ).Else(
+                counter.eq(counter - 1),   
+            ),
+
+            If(check_reset,
+                comma_seen.eq(0),
+            ).Elif((self.data[:10] == comma) | (self.data[:10] == comma_n),
+                comma_seen.eq(1)
+            ),
+
+            one_counts.eq(reduce(add, [self.data[i] for i in range(10)])),
+            If(check_reset,
+                error_seen.eq(0),
+            ).Elif((one_counts != 4) & (one_counts != 5) & (one_counts != 6),
+                error_seen.eq(1),
+            ),
+
+            # DEBUG: 
+            self.has_comma.eq(0),
+            If((self.data[:10] == comma) | (self.data[:10] == comma_n),
+               self.has_comma.eq(1),
+            ),
+
+            self.has_error.eq(0),
+            If((one_counts != 4) & (one_counts != 5) & (one_counts != 6),
+                self.has_error.eq(1),
+            ),
+        ]
+
+        # DEBUG: expose signal
+        self.check_reset = Signal()
+        self.comb +=[
+            self.check_reset.eq(check_reset),
+        ]
+
+        self.submodules.rxfsm = rxfsm = ClockDomainsRenamer("cxp_gtx_rx")(FSM(reset_state="WAIT_COMMA"))
+
+        rxfsm.act("WAIT_COMMA",
+            If(self.comma_det,
+                NextState("ALIGNING"),
+            )
+        )
+
+        rxfsm.act("ALIGNING",
+            If(self.comma_aligned & (~self.comma_realigned),
+                NextState("WAIT_ALIGNED_DATA"),               
+            ).Else(
+                self.aligner_en.eq(1),
+            )
+        )
+
+        # wait for the aligned data to arrive at the FPGA RX interface 
+        # as there is a delay before the data is avaiable after RXBYTEISALIGNED is asserted
+        self.submodules.timer = timer = ClockDomainsRenamer("cxp_gtx_rx")(WaitTimer(10_000))
+
+        rxfsm.act("WAIT_ALIGNED_DATA",
+            timer.wait.eq(1),
+            If(timer.done,
+                check_reset.eq(1),
+                NextState("CHECKING"),
+            )
+        )
+
+        rxfsm.act("CHECKING",
+            If(check,
+                check_reset.eq(1),
+                If(comma_seen & (~error_seen),
+                    NextState("READY"),
+                ).Else(
+                    NextState("WAIT_COMMA")
+                )
+            )
+        )
+
+        ready = Signal()
+        self.specials += MultiReg(ready, self.ready_sys)
+        rxfsm.act("READY",
+            ready.eq(1),
+            If(check,
+                check_reset.eq(1),
+                If(~(comma_seen & (~error_seen)),
+                    NextState("WAIT_COMMA"),
+                )
+            )
+        )
+
+
+class GTX(Module):
+    # Settings:
+    # * GTX reference clock @ 125MHz
+    # * GTX data width = 20
+    # * GTX PLL frequency @ 3.125GHz
+    # * GTX line rate (TX & RX) @ 3.125Gb/s
+    # * GTX TX/RX USRCLK @ PLL/datawidth = 156MHz
+    def __init__(self, qpll, pads, sys_clk_freq, tx_mode="single", rx_mode="single"):
+        assert tx_mode in ["single", "master", "slave"]
+        assert rx_mode in ["single", "master", "slave"]
+
+        # linerate = USRCLK * datawidth
+        pll_fbout_mult = 8
+        txusr_pll_div = pll_fbout_mult*sys_clk_freq/qpll.tx_usrclk_freq
+
+        self.tx_restart = Signal()
+        self.rx_restart = Signal()
+        self.loopback_mode = Signal(3)
+
+        self.txenable = Signal()
+        self.rx_ready = Signal()
+
+        # Dynamic Reconfiguration Ports
+        self.daddr = Signal(9)
+        self.dclk = Signal()
+        self.den = Signal()
+        self.dwen = Signal()
+        self.din = Signal(16)
+        self.dout = Signal(16)
+        self.dready = Signal()
+
+        self.submodules.encoder = ClockDomainsRenamer("cxp_gtx_tx")(Encoder(4, True))
+        self.submodules.decoders = [ClockDomainsRenamer("cxp_gtx_rx")(
+            (Decoder(True))) for _ in range(4)]
+
+
+        # transceiver direct clock outputs
+        # useful to specify clock constraints in a way palatable to Vivado
+        self.txoutclk = Signal()
+        self.rxoutclk = Signal()
+
+        # # #
+
+        # TX generates cxp_tx clock, init must be in system domain
+        # FIXME: 500e6 is used to fix Xx reset by holding gtxXxreset for a couple cycle more
+        self.submodules.tx_init = tx_init = GTXInit(500e6, False, mode=tx_mode)
+        self.submodules.rx_init = rx_init = GTXInit(sys_clk_freq, True, mode=rx_mode)
+
+        # RX receives restart commands from txusrclk domain
+        # self.submodules.rx_init = rx_init = ClockDomainsRenamer("cxp_gtx_tx")(GTXInit(500e6, True, mode=rx_mode))
+
+        self.comb += [
+            tx_init.cplllock.eq(qpll.lock),
+            rx_init.cplllock.eq(qpll.lock)
+        ]
+
+        txdata = Signal(40)
+        rxdata = Signal(40)
+
+        comma_aligned = Signal()
+        comma_realigned = Signal()
+        comma_det = Signal()
+        comma_aligner_en = Signal()
+        # Note: the following parameters were set after consulting AR45360
+        self.specials += \
+            Instance("GTXE2_CHANNEL",
+                # PMA Attributes
+                p_PMA_RSV=0x001E7080,
+                p_PMA_RSV2=0x2050,              # PMA_RSV2[5] = 0: Eye scan feature disabled
+                p_PMA_RSV3=0,
+                p_PMA_RSV4=1,                   # PMA_RSV[4],RX_CM_TRIM[2:0] = 0b1010: Common mode 800mV
+                p_RX_BIAS_CFG=0b000000000100,
+                p_RX_OS_CFG=0b0000010000000,
+                p_RX_CLK25_DIV=5,
+                p_TX_CLK25_DIV=5,
+
+                # Power-Down Attributes
+                p_PD_TRANS_TIME_FROM_P2=0x3c,
+                p_PD_TRANS_TIME_NONE_P2=0x3c,
+                p_PD_TRANS_TIME_TO_P2=0x64,
+                i_CPLLPD=1,
+
+                # QPLL
+                i_QPLLCLK=qpll.clk,
+                i_QPLLREFCLK=qpll.refclk,
+                p_RXOUT_DIV=qpll.Xxout_div,
+                p_TXOUT_DIV=qpll.Xxout_div,
+                i_RXSYSCLKSEL=0b11, # use QPLL & QPLL's REFCLK
+                i_TXSYSCLKSEL=0b11, # use QPLL & CPLL's REFCLK
+
+                # TX clock
+                p_TXBUF_EN="FALSE",
+                p_TX_XCLK_SEL="TXUSR",
+                o_TXOUTCLK=self.txoutclk,
+                # i_TXSYSCLKSEL=0b00,
+                i_TXOUTCLKSEL=0b11,
+
+                # TX Startup/Reset
+                i_TXPHDLYRESET=0,
+                i_TXDLYBYPASS=0,
+                i_TXPHALIGNEN=1 if tx_mode != "single" else 0,
+                i_GTTXRESET=tx_init.gtXxreset,
+                o_TXRESETDONE=tx_init.Xxresetdone,
+                i_TXDLYSRESET=tx_init.Xxdlysreset,
+                o_TXDLYSRESETDONE=tx_init.Xxdlysresetdone,
+                i_TXPHINIT=tx_init.txphinit if tx_mode != "single" else 0,
+                o_TXPHINITDONE=tx_init.txphinitdone if tx_mode != "single" else Signal(),
+                i_TXPHALIGN=tx_init.Xxphalign if tx_mode != "single" else 0,
+                i_TXDLYEN=tx_init.Xxdlyen if tx_mode != "single" else 0,
+                o_TXPHALIGNDONE=tx_init.Xxphaligndone,
+                i_TXUSERRDY=tx_init.Xxuserrdy,
+                p_TXPMARESET_TIME=1,
+                p_TXPCSRESET_TIME=1,
+                i_TXINHIBIT=~self.txenable,
+
+                # TX data
+                p_TX_DATA_WIDTH=40,
+                p_TX_INT_DATAWIDTH=1, # 1 if a line rate is greater than 6.6 Gbps
+                i_TXCHARDISPMODE=Cat(txdata[9], txdata[19], txdata[29], txdata[39]),
+                i_TXCHARDISPVAL=Cat(txdata[8], txdata[18], txdata[28], txdata[38]),
+                i_TXDATA=Cat(txdata[:8], txdata[10:18], txdata[20:28], txdata[30:38]),
+                i_TXUSRCLK=ClockSignal("cxp_gtx_tx"),
+                i_TXUSRCLK2=ClockSignal("cxp_gtx_tx"),
+
+                # TX electrical
+                i_TXBUFDIFFCTRL=0b100,
+                i_TXDIFFCTRL=0b1000,
+
+                # RX Startup/Reset
+                i_RXPHDLYRESET=0,
+                i_RXDLYBYPASS=0,
+                i_RXPHALIGNEN=1 if rx_mode != "single" else 0,
+                i_GTRXRESET=rx_init.gtXxreset,
+                o_RXRESETDONE=rx_init.Xxresetdone,
+                i_RXDLYSRESET=rx_init.Xxdlysreset,
+                o_RXDLYSRESETDONE=rx_init.Xxdlysresetdone,
+                i_RXPHALIGN=rx_init.Xxphalign if rx_mode != "single" else 0,
+                i_RXDLYEN=rx_init.Xxdlyen if rx_mode != "single" else 0,
+                o_RXPHALIGNDONE=rx_init.Xxphaligndone,
+                i_RXUSERRDY=rx_init.Xxuserrdy,
+                p_RXPMARESET_TIME=1,
+                p_RXPCSRESET_TIME=1,
+
+                # RX AFE
+                p_RX_DFE_XYD_CFG=0,
+                p_RX_CM_SEL=0b11,               # RX_CM_SEL = 0b11: Common mode is programmable
+                p_RX_CM_TRIM=0b010,             # PMA_RSV[4],RX_CM_TRIM[2:0] = 0b1010: Common mode 800mV
+                i_RXDFEXYDEN=1,
+                i_RXDFEXYDHOLD=0,
+                i_RXDFEXYDOVRDEN=0,
+                i_RXLPMEN=1,                    # RXLPMEN = 1: LPM mode is enable for non scramble 8b10b data
+                p_RXLPM_HF_CFG=0b00000011110000,
+                p_RXLPM_LF_CFG=0b00000011110000,
+
+                p_RX_DFE_GAIN_CFG=0x0207EA,
+                p_RX_DFE_VP_CFG=0b00011111100000011,
+                p_RX_DFE_UT_CFG=0b10001000000000000,
+                p_RX_DFE_KL_CFG=0b0000011111110,
+                p_RX_DFE_KL_CFG2=0x3788140A,
+                p_RX_DFE_H2_CFG=0b000110000000,
+                p_RX_DFE_H3_CFG=0b000110000000,
+                p_RX_DFE_H4_CFG=0b00011100000,
+                p_RX_DFE_H5_CFG=0b00011100000,
+                p_RX_DFE_LPM_CFG=0x0904,        # RX_DFE_LPM_CFG = 0x0904: linerate <= 6.6Gb/s
+                                                #                = 0x0104: linerate > 6.6Gb/s
+
+                # RX clock
+                i_RXDDIEN=1,
+                # i_RXSYSCLKSEL=0b00,
+                i_RXOUTCLKSEL=0b010,
+                o_RXOUTCLK=self.rxoutclk,
+                i_RXUSRCLK=ClockSignal("cxp_gtx_rx"),
+                i_RXUSRCLK2=ClockSignal("cxp_gtx_rx"),
+
+                # RX Clock Correction Attributes
+                p_CLK_CORRECT_USE="FALSE",
+                p_CLK_COR_SEQ_1_1=0b0100000000,
+                p_CLK_COR_SEQ_2_1=0b0100000000,
+                p_CLK_COR_SEQ_1_ENABLE=0b1111,
+                p_CLK_COR_SEQ_2_ENABLE=0b1111,
+
+                # RX data
+                p_RX_DATA_WIDTH=40,
+                p_RX_INT_DATAWIDTH=1,   # 1 if a line rate is greater than 6.6 Gbps
+                o_RXDISPERR=Cat(rxdata[9], rxdata[19], rxdata[29], rxdata[39]),
+                o_RXCHARISK=Cat(rxdata[8], rxdata[18], rxdata[28], rxdata[38]),
+                o_RXDATA=Cat(rxdata[:8], rxdata[10:18], rxdata[20:28], rxdata[30:38]),
+
+                # RX Byte and Word Alignment Attributes
+                p_ALIGN_COMMA_DOUBLE="FALSE",
+                p_ALIGN_COMMA_ENABLE=0b1111111111,
+                p_ALIGN_COMMA_WORD=4, # align comma to rxdata[:10] only
+                p_ALIGN_MCOMMA_DET="TRUE",
+                p_ALIGN_MCOMMA_VALUE=0b1010000011,
+                p_ALIGN_PCOMMA_DET="TRUE",
+                p_ALIGN_PCOMMA_VALUE=0b0101111100,
+                p_SHOW_REALIGN_COMMA="FALSE",
+                p_RXSLIDE_AUTO_WAIT=7,
+                p_RXSLIDE_MODE="OFF",
+                p_RX_SIG_VALID_DLY=10,
+                i_RXPCOMMAALIGNEN=comma_aligner_en,
+                i_RXMCOMMAALIGNEN=comma_aligner_en,
+                i_RXCOMMADETEN=1,
+                i_RXSLIDE=0,
+                o_RXBYTEISALIGNED=comma_aligned,
+                o_RXBYTEREALIGN=comma_realigned,
+                o_RXCOMMADET=comma_det,
+
+                # RX 8B/10B Decoder Attributes
+                p_RX_DISPERR_SEQ_MATCH="FALSE",
+                p_DEC_MCOMMA_DETECT="TRUE",
+                p_DEC_PCOMMA_DETECT="TRUE",
+                p_DEC_VALID_COMMA_ONLY="FALSE",
+
+                # RX Buffer Attributes
+                p_RXBUF_ADDR_MODE="FAST",
+                p_RXBUF_EIDLE_HI_CNT=0b1000,
+                p_RXBUF_EIDLE_LO_CNT=0b0000,
+                p_RXBUF_EN="FALSE",
+                p_RX_BUFFER_CFG=0b000000,
+                p_RXBUF_RESET_ON_CB_CHANGE="TRUE",
+                p_RXBUF_RESET_ON_COMMAALIGN="FALSE",
+                p_RXBUF_RESET_ON_EIDLE="FALSE",     # RXBUF_RESET_ON_EIDLE = FALSE: OOB is disabled
+                p_RXBUF_RESET_ON_RATE_CHANGE="TRUE",
+                p_RXBUFRESET_TIME=0b00001,
+                p_RXBUF_THRESH_OVFLW=61,
+                p_RXBUF_THRESH_OVRD="FALSE",
+                p_RXBUF_THRESH_UNDFLW=4,
+                p_RXDLY_CFG=0x001F,
+                p_RXDLY_LCFG=0x030,
+                p_RXDLY_TAP_CFG=0x0000,
+                p_RXPH_CFG=0xC00002,
+                p_RXPHDLY_CFG=0x084020,
+                p_RXPH_MONITOR_SEL=0b00000,
+                p_RX_XCLK_SEL="RXUSR",
+                p_RX_DDI_SEL=0b000000,
+                p_RX_DEFER_RESET_BUF_EN="TRUE",
+
+                # CDR Attributes
+                p_RXCDR_CFG=0x03_0000_23FF_1008_0020,   # LPM @ 0.5G-1.5625G , 8B/10B encoded data, CDR setting < +/- 200ppm
+                                                        # (See UG476 (v1.12.1), p.206)
+                p_RXCDR_FR_RESET_ON_EIDLE=0b0,
+                p_RXCDR_HOLD_DURING_EIDLE=0b0,
+                p_RXCDR_PH_RESET_ON_EIDLE=0b0,
+                p_RXCDR_LOCK_CFG=0b010101,
+
+                # Pads
+                i_GTXRXP=pads.rxp,
+                i_GTXRXN=pads.rxn,
+                o_GTXTXP=pads.txp,
+                o_GTXTXN=pads.txn,
+
+                # Dynamic Reconfiguration Ports
+                p_IS_DRPCLK_INVERTED=0b0,
+                i_DRPADDR=self.daddr,
+                i_DRPCLK=self.dclk,
+                i_DRPEN=self.den,
+                i_DRPWE=self.dwen,
+                i_DRPDI=self.din,
+                o_DRPDO=self.dout,
+                o_DRPRDY=self.dready,
+
+                # ! loopback for debugging
+                i_LOOPBACK = self.loopback_mode,
+                p_TX_LOOPBACK_DRIVE_HIZ = "FALSE",
+                p_RXPRBS_ERR_LOOPBACK = 0b0,
+
+                # Other parameters
+                p_PCS_RSVD_ATTR=(
+                    (tx_mode != "single") << 1 |    # PCS_RSVD_ATTR[1] = 0: TX Single Lane Auto Mode
+                                                    #                  = 1: TX Manual Mode
+                    (rx_mode != "single") << 2 |    #              [2] = 0: RX Single Lane Auto Mode
+                                                    #                  = 1: RX Manual Mode
+                    0 << 8                          #              [8] = 0: OOB is disabled
+                ),
+                i_RXELECIDLEMODE=0b11,              # RXELECIDLEMODE = 0b11: OOB is disabled
+                p_RX_DFE_LPM_HOLD_DURING_EIDLE=0b0,
+                p_ES_EYE_SCAN_EN="TRUE",            # Must be TRUE for GTX
+            )
+
+
+        # TX clocking
+        # A PLL is used to generate the correct frequency for TXUSRCLK (UG476 Equation 3-1)
+        self.clock_domains.cd_cxp_gtx_tx = ClockDomain()
+        txpll_fb_clk = Signal()
+        txoutclk_buf = Signal()
+        txpll_clkout = Signal()
+
+        self.txpll_reset = Signal()
+        self.pll_daddr = Signal(7)
+        self.pll_dclk = Signal()
+        self.pll_den = Signal()
+        self.pll_din = Signal(16)
+        self.pll_dwen = Signal()
+
+        self.txpll_locked = Signal()
+        self.pll_dout = Signal(16)
+        self.pll_dready = Signal()
+        self.specials += [
+            Instance("PLLE2_ADV",
+                p_BANDWIDTH="HIGH",
+                o_LOCKED=self.txpll_locked,
+                i_RST=self.txpll_reset,
+                
+                p_CLKIN1_PERIOD=1e9/sys_clk_freq, # ns
+                i_CLKIN1=txoutclk_buf,
+
+                # VCO @ 1.25GHz 
+                p_CLKFBOUT_MULT=pll_fbout_mult, p_DIVCLK_DIVIDE=1,
+                i_CLKFBIN=txpll_fb_clk, o_CLKFBOUT=txpll_fb_clk, 
+
+                # frequency = linerate/40
+                p_CLKOUT0_DIVIDE=txusr_pll_div, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=txpll_clkout,
+
+                # Dynamic Reconfiguration Ports
+                i_DADDR = self.pll_daddr,
+                i_DCLK = self.pll_dclk,
+                i_DEN = self.pll_den,
+                i_DI = self.pll_din,
+                i_DWE = self.pll_dwen,
+                o_DO = self.pll_dout,
+                o_DRDY = self.pll_dready,
+            ),
+            Instance("BUFG", i_I=self.txoutclk, o_O=txoutclk_buf),
+            Instance("BUFG", i_I=txpll_clkout, o_O=self.cd_cxp_gtx_tx.clk),
+            AsyncResetSynchronizer(self.cd_cxp_gtx_tx, ~self.txpll_locked & ~tx_init.done)
+        ]
+
+        # RX clocking
+        # the CDR matches the required frequency for RXUSRCLK, no need for PLL 
+        self.clock_domains.cd_cxp_gtx_rx = ClockDomain()
+        self.specials += [
+            Instance("BUFG", i_I=self.rxoutclk, o_O=self.cd_cxp_gtx_rx.clk),
+            AsyncResetSynchronizer(self.cd_cxp_gtx_rx, ~rx_init.done)
+        ]
+
+        self.comb += [
+            txdata.eq(Cat(self.encoder.output[0], self.encoder.output[1], self.encoder.output[2], self.encoder.output[3])),
+            self.decoders[0].input.eq(rxdata[:10]),
+            self.decoders[1].input.eq(rxdata[10:20]),
+            self.decoders[2].input.eq(rxdata[20:30]),
+            self.decoders[3].input.eq(rxdata[30:]),
+        ]
+
+
+        self.submodules.comma_checker = comma_checker = Comma_Checker(0b0101111100)
+        self.comb += [
+            comma_checker.data.eq(rxdata),
+            comma_checker.comma_aligned.eq(comma_aligned),
+            comma_checker.comma_realigned.eq(comma_realigned),
+            comma_checker.comma_det.eq(comma_det),
+            comma_aligner_en.eq(comma_checker.aligner_en),
+            self.rx_ready.eq(comma_checker.ready_sys),
+
+            rx_init.restart.eq(self.rx_restart | comma_checker.restart_sys),
+            tx_init.restart.eq(self.tx_restart),
+        ]

src/gateware/cxp_pipeline.py

@@ -0,0 +1,450 @@
+from migen import *
+from misoc.interconnect.csr import *
+from misoc.interconnect import stream
+
+char_width = 8
+char_layout = [("data", char_width), ("k", char_width//8)]
+
+word_dw = 32
+word_layout = [("data", word_dw), ("k", word_dw//8)]
+buffer_depth = 128
+
+def K(x, y):
+    return ((y << 5) | x)
+
+KCode = {
+    "pak_start" : C(K(27, 7), char_width),
+    "io_ack" : C(K(28, 6), char_width), 
+    "trig_indic_28_2" : C(K(28, 2), char_width),
+    "trig_indic_28_4" : C(K(28, 4), char_width),
+    "pak_end" : C(K(29, 7), char_width),
+    "idle_comma" : C(K(28, 5), char_width),
+    "idle_alignment" : C(K(28, 1), char_width),
+}
+
+class Packet_Wrapper(Module):
+    def __init__(self):
+        self.sink = stream.Endpoint(word_layout)
+        self.source = stream.Endpoint(word_layout)
+
+        # # #
+
+        self.submodules.fsm = fsm = FSM(reset_state="IDLE")
+        
+        fsm.act("IDLE",
+            self.sink.ack.eq(1),
+            If(self.sink.stb,
+                self.sink.ack.eq(0),
+                NextState("INSERT_HEADER"),
+            )
+        )
+
+        fsm.act("INSERT_HEADER",
+            self.sink.ack.eq(0),
+            self.source.stb.eq(1),
+            self.source.data.eq(Replicate(KCode["pak_start"], 4)),
+            self.source.k.eq(0b1111),
+            If(self.source.ack, NextState("COPY")),
+        )
+
+        fsm.act("COPY",
+            self.sink.connect(self.source),
+            self.source.eop.eq(0),
+            If(self.sink.stb & self.sink.eop & self.source.ack,
+                NextState("INSERT_FOOTER"),
+            ),
+        )
+
+        fsm.act("INSERT_FOOTER",
+            self.sink.ack.eq(0),
+            self.source.stb.eq(1),
+            self.source.data.eq(Replicate(KCode["pak_end"], 4)),
+            self.source.k.eq(0b1111),
+            self.source.eop.eq(1),
+            If(self.source.ack, NextState("IDLE")),
+        )
+        
+class TX_Trigger(Module):
+    def __init__(self):
+        self.stb = Signal()
+        self.delay = Signal(char_width) 
+        self.linktrig_mode = Signal(max=4)
+
+        # # #
+
+        self.sink = stream.Endpoint(char_layout)
+        self.source = stream.Endpoint(char_layout)
+
+        # Table 15 & 16 (CXP-001-2021)
+        # Send [K28.2, K28.4, K28.4] or [K28.4, K28.2, K28.2] and 3x delay as trigger packet 
+
+        trig_packet = [Signal(char_width), Signal(char_width), Signal(char_width), self.delay, self.delay, self.delay]
+        trig_packet_k = [1, 1, 1, 0, 0, 0]
+        self.comb += [
+            If((self.linktrig_mode == 0) | (self.linktrig_mode == 2),
+                trig_packet[0].eq(KCode["trig_indic_28_2"]),
+                trig_packet[1].eq(KCode["trig_indic_28_4"]),
+                trig_packet[2].eq(KCode["trig_indic_28_4"]),
+            ).Else(
+                trig_packet[0].eq(KCode["trig_indic_28_4"]),
+                trig_packet[1].eq(KCode["trig_indic_28_2"]),
+                trig_packet[2].eq(KCode["trig_indic_28_2"]),
+            ),
+        ]
+        
+        self.submodules.fsm = fsm = FSM(reset_state="COPY")
+        
+        cnt = Signal(max=6)
+        fsm.act("COPY",
+            NextValue(cnt, cnt.reset),
+            self.sink.connect(self.source),
+            If(self.stb, NextState("WRITE_TRIG"))
+        )
+
+        fsm.act("WRITE_TRIG",
+            self.sink.ack.eq(0),
+            self.source.stb.eq(1),
+            self.source.data.eq(Array(trig_packet)[cnt]),
+            self.source.k.eq(Array(trig_packet_k)[cnt]),
+            If(self.source.ack,
+                If(cnt == 5,
+                    NextState("COPY"),
+                ).Else(
+                    NextValue(cnt, cnt + 1),
+                )
+            )
+        )
+
+class Idle_Word_Inserter(Module):
+    def __init__(self):
+        self.stb = Signal()
+
+        # # #
+
+        # Section 9.2.5 (CXP-001-2021)
+        # Send K28.5, K28.1, K28.1, D21.5  as idle word
+        self.submodules.fsm = fsm = FSM(reset_state="COPY")
+        
+        self.sink = stream.Endpoint(word_layout)
+        self.source = stream.Endpoint(word_layout)
+        fsm.act("COPY",
+            self.sink.connect(self.source),
+            If(self.stb, NextState("WRITE_IDLE"))
+        )
+
+        fsm.act("WRITE_IDLE",
+            self.sink.ack.eq(0),
+            self.source.stb.eq(1),
+            self.source.data.eq(Cat(KCode["idle_comma"], KCode["idle_alignment"], KCode["idle_alignment"], C(0xB5, char_width))),
+            self.source.k.eq(0b1110),
+            If(self.source.ack, NextState("COPY")),
+        )
+
+
+class Trigger_ACK_Inserter(Module):
+    def __init__(self):
+        self.stb = Signal()
+
+        # # #
+
+        # Section 9.3.2 (CXP-001-2021)
+        # Send 4x K28.6 and 4x 0x01 as trigger packet ack
+        self.submodules.fsm = fsm = FSM(reset_state="COPY")
+        
+        self.sink = stream.Endpoint(word_layout)
+        self.source = stream.Endpoint(word_layout)
+        fsm.act("COPY",
+            self.sink.connect(self.source),
+            If(self.stb, NextState("WRITE_ACK0"))
+        )
+
+        fsm.act("WRITE_ACK0",
+            self.sink.ack.eq(0),
+            self.source.stb.eq(1),
+            self.source.data.eq(Replicate(KCode["io_ack"], 4)),
+            self.source.k.eq(0b1111),
+            If(self.source.ack, NextState("WRITE_ACK1")),
+        )
+
+        fsm.act("WRITE_ACK1",
+            self.sink.ack.eq(0),
+            self.source.stb.eq(1),
+            self.source.data.eq(Replicate(C(0x01, char_width), 4)),
+            self.source.k.eq(0b0000),
+            If(self.source.ack, NextState("COPY")),
+        )
+
+
+@FullMemoryWE()
+class TX_Command_Packet(Module, AutoCSR):
+    def __init__(self):
+        self.tx_word_len = CSRStorage(bits_for(buffer_depth))
+        self.tx = CSR()
+
+        # # #
+        
+        self.specials.mem = mem = Memory(word_dw, buffer_depth)
+        self.specials.mem_port = mem_port = mem.get_port()
+        self.source = stream.Endpoint(word_layout)
+
+
+        tx_done = Signal()
+        addr_next = Signal(bits_for(buffer_depth))
+        addr = Signal.like(addr_next)
+        addr_rst = Signal()
+        addr_inc = Signal()
+
+        # increment addr in the same cycle the moment addr_inc is high
+        # as memory takes one cycle to shift to the correct addr
+        self.sync += [
+            addr.eq(addr_next),
+            If(self.tx.re, self.tx.w.eq(1)),
+            If(tx_done, self.tx.w.eq(0)),
+        ]
+
+        self.comb += [
+            addr_next.eq(addr),
+            If(addr_rst,
+                addr_next.eq(addr_next.reset),
+            ).Elif(addr_inc,
+                addr_next.eq(addr + 1),
+            ),
+            mem_port.adr.eq(addr_next),
+            self.source.data.eq(mem_port.dat_r)
+        ]
+
+        self.submodules.fsm = fsm = FSM(reset_state="IDLE")
+
+        fsm.act("IDLE",
+            addr_rst.eq(1),
+            If(self.tx.re, NextState("TRANSMIT"))
+        )
+        fsm.act("TRANSMIT",
+            self.source.stb.eq(1),
+            If(self.source.ack,
+                addr_inc.eq(1),
+            ),
+            If(addr_next == self.tx_word_len.storage,
+                self.source.eop.eq(1),
+                tx_done.eq(1),
+                NextState("IDLE")
+            )
+        )
+
+class TX_Test_Packet(Module, AutoCSR):
+    def __init__(self):
+        self.tx = CSR()
+
+        # # #
+        
+        tx_done = Signal()
+        self.sync += [
+            If(self.tx.re, self.tx.w.eq(1)),
+            If(tx_done, self.tx.w.eq(0)),
+        ]
+
+        self.source = stream.Endpoint(word_layout)
+        self.submodules.fsm = fsm = FSM(reset_state="IDLE")
+        
+        cnt = Signal(0xFFF)
+        fsm.act("IDLE",
+            NextValue(cnt, cnt.reset),
+            If(self.tx.re,
+               NextState("WRITE_PACKET_TYPE")
+            )
+        )
+
+        fsm.act("WRITE_PACKET_TYPE",
+            self.source.stb.eq(1),
+            self.source.data.eq(Replicate(C(0x04, char_width), 4)),
+            self.source.k.eq(0b0000),
+            If(self.source.ack,NextState("WRITE_TEST_COUNTER"))
+        )
+
+        fsm.act("WRITE_TEST_COUNTER",
+            self.source.stb.eq(1),
+            self.source.data.eq(Cat(cnt[:8], cnt[:8]+1, cnt[:8]+2, cnt[:8]+3)),
+            self.source.k.eq(0b0000),
+            If(self.source.ack,
+                If(cnt == 0xFFF-3,
+                    tx_done.eq(1),
+                    self.source.eop.eq(1),
+                    NextState("IDLE")
+                ).Else(
+                    NextValue(cnt, cnt + 4),
+                )
+               
+            )
+        )
+
+
+
+class RX_Debug_Buffer(Module,AutoCSR):
+    def __init__(self):
+        self.submodules.buf_out = buf_out = stream.SyncFIFO(word_layout, 128)
+        self.sink = buf_out.sink
+
+        self.inc = CSR()
+        self.dout_pak = CSRStatus(word_dw)
+        self.kout_pak = CSRStatus(word_dw//8)
+        self.dout_valid = CSRStatus()
+
+        self.sync += [
+            # output
+            buf_out.source.ack.eq(self.inc.re),
+            self.dout_pak.status.eq(buf_out.source.data),
+            self.kout_pak.status.eq(buf_out.source.k),
+            self.dout_valid.status.eq(buf_out.source.stb),
+        ]
+
+@FullMemoryWE()
+class CXP_Data_Packet_Decode(Module):
+    def __init__(self):
+        self.packet_type = Signal(8)
+        self.write_ptr = Signal(bits_for(buffer_depth))
+
+        self.new_packet = Signal()
+        self.decode_err = Signal()
+        self.test_err = Signal()
+        # # #
+
+        # DEBUG: remove debug
+        # TODO: decode all packet type here
+        # TODO: data&event -> memory
+        # TODO: heartbeat
+        type = {
+            "data_stream": 0x01,
+            "control_ack_no_tag": 0x03,
+            "test_packet": 0x04,
+            "control_ack_with_tag": 0x06,
+            "event": 0x07,
+            "heartbeat": 0x09,
+
+            "debug" : 0x02,
+        }
+
+        self.sink = stream.Endpoint(word_layout)
+        self.source = stream.Endpoint(word_layout)
+
+        self.submodules.fsm = fsm = FSM(reset_state="IDLE")
+
+        fsm.act("IDLE",
+            self.sink.ack.eq(1),
+            # TODO: add error correction?
+            If((self.sink.stb & (self.sink.data == Replicate(KCode["pak_start"], 4)) & (self.sink.k == 0b1111)),
+                NextState("DECODE"),
+            )
+        )
+
+        cnt = Signal(max=0x100)
+        fsm.act("DECODE",
+            self.sink.ack.eq(1),
+            If(self.sink.stb,
+                self.new_packet.eq(1),
+                NextValue(self.packet_type, self.sink.data[:8]),
+
+                Case(self.sink.data[:8],{
+                    type["data_stream"]: NextState("STREAMING"),
+                    type["control_ack_no_tag"]: NextState("LOAD_BUFFER"),
+                    type["test_packet"]: [
+                        NextValue(cnt, cnt.reset),
+                        NextState("VERIFY_TEST_PATTERN"),
+                    ],
+                    type["control_ack_with_tag"]: NextState("LOAD_BUFFER"),
+                    type["event"]: NextState("LOAD_BUFFER"),
+
+                    type["debug"]: NextState("LOAD_BUFFER"),
+                    "default": [
+                         self.decode_err.eq(1),
+                         # wait till next valid packet
+                         NextState("IDLE"),
+                    ],
+                }),
+            )
+        )
+
+        # Section 9.9.1 (CXP-001-2021)
+        # the received test data packet (0x00, 0x01 ... 0xFF) 
+        # need to be compared against the local test sequence generator
+        fsm.act("VERIFY_TEST_PATTERN",
+            self.sink.ack.eq(1),
+            If(self.sink.stb,
+                If(((self.sink.data == Replicate(KCode["pak_end"], 4)) & (self.sink.k == 0b1111)),
+                    NextState("IDLE"),
+                ).Else(
+                    If(((self.sink.data != Cat(cnt, cnt+1, cnt+2, cnt+3))),  
+                        self.test_err.eq(1),
+                    ),
+                    If(cnt == 0xFC,
+                        NextValue(cnt, cnt.reset),
+                    ).Else(
+                        NextValue(cnt, cnt + 4)
+                    )
+                )
+            )
+                
+        )
+
+        # For stream data packet
+        fsm.act("STREAMING",
+            If((self.sink.stb & (self.sink.data == Replicate(KCode["pak_end"], 4)) & (self.sink.k == 0b1111)),
+                # discard K29,7
+                self.sink.ack.eq(1),
+                NextState("IDLE")
+            ).Else(
+                self.sink.connect(self.source),
+            )      
+        )
+
+        # A circular buffer for firmware to read packet from
+        self.specials.mem = mem = Memory(word_dw, buffer_depth)
+        self.specials.mem_port = mem_port = mem.get_port(write_capable=True)
+
+        self.comb += mem_port.adr.eq(self.write_ptr),
+
+        # For control ack, event packet
+        fsm.act("LOAD_BUFFER",
+            mem_port.we.eq(0),
+            self.sink.ack.eq(1),
+            If(self.sink.stb,
+                If(((self.sink.data == Replicate(KCode["pak_end"], 4)) & (self.sink.k == 0b1111)),
+                    NextState("IDLE"),
+                ).Else(
+                    mem_port.we.eq(1),
+                    mem_port.dat_w.eq(self.sink.data),
+                    NextValue(self.write_ptr, self.write_ptr + 1),
+                )
+            )
+        )
+
+class CXP_Trig_Ack_Checker(Module, AutoCSR):
+    def __init__(self):
+        self.sink = stream.Endpoint(word_layout)
+        self.source = stream.Endpoint(word_layout)
+
+        self.ack = Signal()
+
+        # # #
+
+        self.submodules.fsm = fsm = FSM(reset_state="COPY")
+
+        fsm.act("COPY",
+            If((self.sink.stb & (self.sink.data == Replicate(KCode["io_ack"], 4)) & (self.sink.k == 0b1111)),
+                # discard K28,6
+                self.sink.ack.eq(1),
+                NextState("CHECK_ACK")
+            ).Else(
+                self.sink.connect(self.source),
+            )
+        )
+
+        fsm.act("CHECK_ACK",
+            If(self.sink.stb,
+                NextState("COPY"),
+                # discard the word after K28,6
+                self.sink.ack.eq(1),
+                If(self.sink.data == Replicate(C(0x01, char_width), 4),
+                    self.ack.eq(1),
+                )
+            )
+        )

src/gateware/cxp_upconn.py

@@ -0,0 +1,212 @@
+from math import ceil
+
+from migen import *
+
+from misoc.cores.code_8b10b import SingleEncoder
+from misoc.interconnect import stream
+from misoc.interconnect.csr import *
+
+from cxp_pipeline import char_layout
+
+@ResetInserter()
+class UpConn_ClockGen(Module):
+    def __init__(self, sys_clk_freq):
+        self.clk = Signal()
+        self.clk_10x = Signal() # 20.83MHz 48ns or 41.66MHz 24ns
+
+        self.freq2x_enable = Signal()
+        # # #
+
+        period = 1e9/sys_clk_freq
+        max_count = ceil(48/period)
+        counter = Signal(max=max_count, reset=max_count-1)
+
+        clk_div = Signal(max=10, reset=9)
+
+        self.sync += [
+            self.clk.eq(0),
+            self.clk_10x.eq(0),
+
+            If(counter == 0,
+                self.clk_10x.eq(1),
+                If(self.freq2x_enable,
+                    counter.eq(int(max_count/2)-1),
+                ).Else(
+                    counter.eq(counter.reset),
+                ),
+            ).Else(
+                counter.eq(counter-1),
+            ),
+
+            If(counter == 0,
+                If(clk_div == 0,
+                    self.clk.eq(1),
+                    clk_div.eq(clk_div.reset),
+                ).Else(
+                    clk_div.eq(clk_div-1),
+                )
+            )
+
+        ]
+
+@ResetInserter()
+@CEInserter()
+class SERDES_10bits(Module):
+    def __init__(self, pad):
+        self.oe = Signal()
+        self.d = Signal(10)
+
+        # # #
+
+        o = Signal()
+        tx_bitcount = Signal(max=10)
+        tx_reg = Signal(10)
+
+        # DEBUG:
+        self.o = Signal()
+        self.comb += self.o.eq(o)
+
+        self.specials += Instance("OBUF", i_I=o, o_O=pad),
+        
+        self.sync += [
+            If(self.oe,
+                # send LSB first
+                o.eq(tx_reg[0]),
+                tx_reg.eq(Cat(tx_reg[1:], 0)),
+                tx_bitcount.eq(tx_bitcount + 1),   
+
+                If(tx_bitcount == 9,
+                    tx_bitcount.eq(0),
+                    tx_reg.eq(self.d),
+                ),
+            ).Else(
+                o.eq(0),
+                tx_bitcount.eq(0),
+            )
+        ]
+
+class Debug_buffer(Module,AutoCSR):
+    def __init__(self, layout):
+        self.sink_stb = Signal()
+        self.sink_ack = Signal()
+        self.sink_data = Signal(8)
+        self.sink_k = Signal()
+
+        # # #
+
+        self.submodules.buf_out = buf_out = stream.SyncFIFO(layout, 512)
+
+        self.sync += [
+            buf_out.sink.stb.eq(self.sink_stb),
+            self.sink_ack.eq(buf_out.sink.ack),
+            buf_out.sink.data.eq(self.sink_data),
+            buf_out.sink.k.eq(self.sink_k),
+        ]
+
+        self.inc = CSR()
+        self.dout_pak = CSRStatus(8)
+        self.kout_pak = CSRStatus()
+        self.dout_valid = CSRStatus()
+
+        self.sync += [
+            # output
+            buf_out.source.ack.eq(self.inc.re),
+            self.dout_pak.status.eq(buf_out.source.data),
+            self.kout_pak.status.eq(buf_out.source.k),
+            self.dout_valid.status.eq(buf_out.source.stb),
+        ]
+
+
+class Transmitter(Module, AutoCSR):
+    def __init__(self, pad, sys_clk_freq, debug_sma, pmod_pads):
+        self.bitrate2x_enable = Signal()
+        self.clk_reset = Signal()
+        self.tx_enable = Signal()
+
+        # # #
+
+        self.sink = stream.Endpoint(char_layout)
+
+        self.submodules.cg = cg = UpConn_ClockGen(sys_clk_freq)
+        self.submodules.encoder = encoder = SingleEncoder(True)
+        self.submodules.debug_buf = debug_buf = Debug_buffer(char_layout)
+
+        oe = Signal()
+        self.sync += [
+            If(self.tx_enable,
+                self.sink.ack.eq(0),
+
+                # DEBUG:
+                debug_buf.sink_stb.eq(0),
+
+                If(cg.clk,
+                    oe.eq(1),
+                    encoder.disp_in.eq(encoder.disp_out),
+                    self.sink.ack.eq(1),
+                    encoder.d.eq(self.sink.data),
+                    encoder.k.eq(self.sink.k),
+
+                    # DEBUG:
+                    If(debug_buf.sink_ack,
+                        debug_buf.sink_stb.eq(1),
+                        debug_buf.sink_data.eq(self.sink.data),
+                        debug_buf.sink_k.eq(self.sink.k),
+                    )
+                )
+            ).Else(
+                # DEBUG:
+                debug_buf.sink_stb.eq(0),
+
+                # no backpressure
+                self.sink.ack.eq(1),
+                oe.eq(0),
+            )
+        ]
+
+        self.submodules.serdes = serdes = SERDES_10bits(pad)
+
+        self.comb += [
+            cg.reset.eq(self.clk_reset),
+            cg.freq2x_enable.eq(self.bitrate2x_enable),
+
+            serdes.reset.eq(self.clk_reset),
+            serdes.ce.eq(cg.clk_10x),
+            serdes.d.eq(encoder.output),
+            serdes.oe.eq(oe),
+        ]
+
+        # DEBUG: remove pads
+       
+        self.specials += [
+            # # debug sma
+            # Instance("OBUF", i_I=serdes.o, o_O=debug_sma.p_tx),
+            # Instance("OBUF", i_I=cg.clk_10x, o_O=debug_sma.n_rx),
+
+
+
+            # # pmod 0-7 pin
+            # Instance("OBUF", i_I=serdes.o, o_O=pmod_pads[0]),
+            # Instance("OBUF", i_I=cg.clk_10x, o_O=pmod_pads[1]),
+            # Instance("OBUF", i_I=~tx_fifos.pe.n, o_O=pmod_pads[2]),
+            # Instance("OBUF", i_I=prioity_0, o_O=pmod_pads[3]),
+            # Instance("OBUF", i_I=word_bound, o_O=pmod_pads[4]),
+            # Instance("OBUF", i_I=debug_buf.buf_out.sink.stb, o_O=pmod_pads[4]),
+            # Instance("OBUF", i_I=debug_buf.buf_out.sink.ack, o_O=pmod_pads[5]),
+            # Instance("OBUF", i_I=debug_buf.buf_out.source.stb, o_O=pmod_pads[6]),
+            # Instance("OBUF", i_I=debug_buf.buf_out.source.ack, o_O=pmod_pads[7]),
+
+            # Instance("OBUF", i_I=scheduler.idling, o_O=pmod_pads[5]),
+            # # Instance("OBUF", i_I=tx_fifos.source_ack[0], o_O=pmod[6]),
+            # # Instance("OBUF", i_I=tx_fifos.source_ack[2], o_O=pmod[6]),
+            # # Instance("OBUF", i_I=tx_fifos.source_ack[1], o_O=pmod[7]),
+            # Instance("OBUF", i_I=p0, o_O=pmod_pads[6]),
+            # Instance("OBUF", i_I=p3, o_O=pmod_pads[7]),
+        ]
+
+class CXP_UpConn_PHYS(Module, AutoCSR):
+    def __init__(self, pads, sys_clk_freq, debug_sma, pmod_pads):
+        self.tx_phys = []
+        for i, pad in enumerate(pads):
+            tx = Transmitter(pad, sys_clk_freq, debug_sma, pmod_pads)
+            self.tx_phys.append(tx)
+            setattr(self.submodules, "tx"+str(i), tx)

src/gateware/zc706.py

@@ -25,6 +25,8 @@ import analyzer
 import acpki
 import drtio_aux_controller
 import zynq_clocking
+import cxp_4r_fmc
+import cxp
 from config import write_csr_file, write_mem_file, write_rustc_cfg_file
 
 class SMAClkinForward(Module):
@@ -138,7 +140,7 @@ class ZC706(SoCCore):
         platform.add_extension(si5324_fmc33)
         self.comb += platform.request("si5324_33").rst_n.eq(1)
 
-        cdr_clk = Signal()
+        self.cdr_clk = Signal()
         cdr_clk_buf = Signal()
         si5324_out = platform.request("si5324_clkout")
         platform.add_period_constraint(si5324_out.p, 8.0)
@@ -146,11 +148,11 @@ class ZC706(SoCCore):
             Instance("IBUFDS_GTE2",
                 i_CEB=0,
                 i_I=si5324_out.p, i_IB=si5324_out.n,
-                o_O=cdr_clk,
+                o_O=self.cdr_clk,
                 p_CLKCM_CFG="TRUE",
                 p_CLKRCV_TRST="TRUE",
                 p_CLKSWING_CFG=3),
-            Instance("BUFG", i_I=cdr_clk, o_O=cdr_clk_buf)
+            Instance("BUFG", i_I=self.cdr_clk, o_O=cdr_clk_buf)
         ]
         self.config["HAS_SI5324"] = None
         self.config["SI5324_AS_SYNTHESIZER"] = None
@@ -652,6 +654,118 @@ class _NIST_QC2_RTIO:
         self.add_rtio(rtio_channels)
 
 
+class CXP_FMC():
+    """
+    CoaXpress FMC with 4 CXP channel and 1 SMA trigger
+    """
+    def __init__(self):
+        platform = self.platform
+        platform.add_extension(cxp_4r_fmc.fmc_adapter_io)
+        platform.add_extension(leds_fmc33)
+
+        debug_sma = [
+            ("user_sma_clock_33", 0,
+                Subsignal("p_tx", Pins("AD18"), IOStandard("LVCMOS33")),
+                Subsignal("n_rx", Pins("AD19"), IOStandard("LVCMOS33")),
+            ),
+        ]
+
+        pmod1_33 = [
+            ("pmod1_33", 0, Pins("AJ21"), IOStandard("LVCMOS33")),
+            ("pmod1_33", 1, Pins("AK21"), IOStandard("LVCMOS33")),
+            ("pmod1_33", 2, Pins("AB21"), IOStandard("LVCMOS33")),
+            ("pmod1_33", 3, Pins("AB16"), IOStandard("LVCMOS33")),
+            ("pmod1_33", 4, Pins("Y20"), IOStandard("LVCMOS33")),
+            ("pmod1_33", 5, Pins("AA20"), IOStandard("LVCMOS33")),
+            ("pmod1_33", 6, Pins("AC18"), IOStandard("LVCMOS33")),
+            ("pmod1_33", 7, Pins("AC19"), IOStandard("LVCMOS33")),
+        ]
+
+        platform.add_extension(debug_sma)
+        platform.add_extension(pmod1_33)
+        debug_sma_pad = platform.request("user_sma_clock_33") 
+        pmod_pads = [platform.request("pmod1_33", i) for i in range(8)]
+
+        clk_freq = 125e6
+
+        links = 1
+        cxp_downconn_pads = [platform.request("CXP_HS", i) for i in range(links)]
+        cxp_upconn_pads = [platform.request("CXP_LS", i) for i in range(links)]
+
+
+        self.submodules.cxp_phys = cxp_phys = cxp.CXP_PHYS(
+            refclk=self.cdr_clk,
+            upconn_pads=cxp_upconn_pads,
+            downconn_pads=cxp_downconn_pads,
+            sys_clk_freq=clk_freq,
+            debug_sma=debug_sma_pad,
+            pmod_pads = pmod_pads
+        )
+        self.csr_devices.append("cxp_phys")
+
+
+        cxp_csr_group = []
+        cxp_tx_mem_group = []
+        cxp_rx_mem_group = []
+        cxp_loopback_mem_group = []
+        for i, (tx, rx) in enumerate(zip(cxp_phys.upconn.tx_phys, cxp_phys.downconn.rx_phys)):
+            cxp_name = "cxp" + str(i)
+
+            # TODO: cdr = ClockDomainsRenamer({"cxp_gtx_rx": "cxp_gtx_rx" + str(i)})
+            
+            cxp_interface = cxp.CXP_Interface(tx, rx, debug_sma_pad, pmod_pads)
+            setattr(self.submodules, cxp_name, cxp_interface )
+            self.csr_devices.append(cxp_name)
+            cxp_csr_group.append(cxp_name)
+            
+
+            mem_size = cxp_interface .get_mem_size()
+
+            tx_mem_name = "cxp_tx" + str(i) + "_mem"
+            memory_address = self.axi2csr.register_port(cxp_interface.get_tx_port(), mem_size)
+            self.add_memory_region(tx_mem_name, self.mem_map["csr"] + memory_address, mem_size)
+            cxp_tx_mem_group.append(tx_mem_name)
+
+            rx_mem_name = "cxp_rx" + str(i) + "_mem"
+            memory_address = self.axi2csr.register_port(cxp_interface.get_rx_port(), mem_size)
+            self.add_memory_region(rx_mem_name, self.mem_map["csr"] + memory_address, mem_size)
+            cxp_rx_mem_group.append(rx_mem_name)
+
+
+            # DEBUG loopback tx memory
+            loopback_mem_name = "cxp_loopback_tx" + str(i) + "_mem"
+            cxp_loopback_mem_group.append(loopback_mem_name)
+            memory_address = self.axi2csr.register_port(cxp_interface.get_loopback_tx_port(), mem_size)
+            self.add_memory_region(loopback_mem_name, self.mem_map["csr"] + memory_address, mem_size)
+
+        self.add_memory_group("cxp_tx_mem", cxp_tx_mem_group)
+        self.add_memory_group("cxp_rx_mem", cxp_rx_mem_group)
+        self.add_memory_group("cxp_loopback_mem", cxp_loopback_mem_group)
+        self.add_csr_group("cxp", cxp_csr_group)
+
+        # max freq of cxp_gtx_rx = linerate/internal_datawidth = 12.5Gbps/40 = 312.5MHz
+        # zc706 use speed grade 2 which only support up to 10.3125Gbps (4ns)
+        # pushing to 12.5Gbps (3.2ns) will result in Pulse width violation but setup/hold times are met
+        for rx in cxp_phys.downconn.rx_phys :
+            platform.add_period_constraint(rx.gtx.cd_cxp_gtx_tx.clk, 3.2)
+            platform.add_period_constraint(rx.gtx.cd_cxp_gtx_rx.clk, 3.2)
+            # constraint the CLK path 
+            platform.add_false_path_constraints(self.sys_crg.cd_sys.clk, rx.gtx.cd_cxp_gtx_tx.clk, rx.gtx.cd_cxp_gtx_rx.clk)
+
+        rtio_channels = []
+        # FIXME remove this placeholder RTIO channel
+        # There are too few RTIO channels and cannot be compiled (adr width issue of the lane distributor)
+        # see https://github.com/m-labs/artiq/pull/2158 for similar issue
+        print("USER LED at RTIO channel 0x{:06x}".format(len(rtio_channels)))
+        phy = ttl_simple.Output(self.platform.request("user_led_33", 0))
+        self.submodules += phy
+        rtio_channels.append(rtio.Channel.from_phy(phy))
+        self.config["HAS_RTIO_LOG"] = None
+        rtio_channels.append(rtio.LogChannel())
+
+        self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
+        self.add_rtio(rtio_channels)
+
 class NIST_CLOCK(ZC706, _NIST_CLOCK_RTIO):
     def __init__(self, acpki, drtio100mhz):
         ZC706.__init__(self, acpki)
@@ -684,8 +798,13 @@ class NIST_QC2_Satellite(_SatelliteBase, _NIST_QC2_RTIO):
         _SatelliteBase.__init__(self, acpki, drtio100mhz)
         _NIST_QC2_RTIO.__init__(self)
 
+class CXP_Demo(ZC706, CXP_FMC):
+    def __init__(self, acpki, drtio100mhz):
+        ZC706.__init__(self, acpki)
+        CXP_FMC.__init__(self)
+
 VARIANTS = {cls.__name__.lower(): cls for cls in [NIST_CLOCK, NIST_CLOCK_Master, NIST_CLOCK_Satellite,
-                                                  NIST_QC2, NIST_QC2_Master, NIST_QC2_Satellite]}
+                                                  NIST_QC2, NIST_QC2_Master, NIST_QC2_Satellite, CXP_Demo]}
 
 def main():
     parser = argparse.ArgumentParser(

src/libboard_artiq/src/cxp_downconn.rs

@@ -0,0 +1,520 @@
+use embedded_hal::prelude::_embedded_hal_blocking_delay_DelayUs;
+use libboard_zynq::{println, timer::GlobalTimer};
+use log::info;
+
+// use log::info;
+use crate::{cxp_proto,
+            pl::{csr, csr::CXP}};
+
+#[derive(Clone, Copy, Debug)]
+#[allow(non_camel_case_types)]
+pub enum CXP_SPEED {
+    CXP_1,
+    CXP_2,
+    CXP_3,
+    CXP_5,
+    CXP_6,
+    CXP_10,
+    CXP_12,
+}
+
+pub fn loopback_testing(channel: usize, timer: &mut GlobalTimer, speed: CXP_SPEED) {
+    println!("==============================================================================");
+    cxp_gtx::change_linerate(channel, timer, speed);
+
+    unsafe {
+        info!("waiting for tx&rx setup...");
+        timer.delay_us(50_000);
+        info!(
+            "tx_phaligndone = {} | rx_phaligndone = {}",
+            (CXP[channel].downconn_txinit_phaligndone_read)(),
+            (CXP[channel].downconn_rxinit_phaligndone_read)(),
+        );
+
+        // enable txdata tranmission thought MGTXTXP, required by PMA loopback
+        (CXP[channel].downconn_txenable_write)(1);
+
+        info!("waiting for rx to align...");
+        while (CXP[channel].downconn_rx_ready_read)() != 1 {}
+        info!("rx ready!");
+
+        (CXP[channel].downconn_tx_stb_write)(1);
+        cxp_proto::downconn_send_test_packet(channel);
+
+        cxp_proto::downconn_debug_send_trig_ack(channel);
+
+        cxp_proto::downconn_debug_send(
+            channel,
+            &cxp_proto::Packet::CtrlRead {
+                addr: 0x00,
+                length: 0x04,
+            },
+        )
+        .expect("loopback gtx tx error");
+
+        timer.delay_us(200); // wait packet has arrive at RX async fifo
+        (CXP[channel].downconn_tx_stb_write)(0);
+
+        info!("trig ack = {}", (CXP[channel].downconn_trigger_ack_read)());
+        (CXP[channel].downconn_trigger_ack_write)(1);
+        info!("after clr trig ack = {}", (CXP[channel].downconn_trigger_ack_read)());
+
+        info!("decoder error = {}", (CXP[channel].downconn_decoder_error_read)());
+        info!("test error = {}", (CXP[channel].downconn_test_error_read)());
+        info!("packet type = {:#06X}", (CXP[channel].downconn_packet_type_read)());
+
+        cxp_proto::receive(channel);
+        // DEBUG: print loopback packets
+        const LEN: usize = 20;
+        let mut pak_arr: [u32; LEN] = [0; LEN];
+        let mut k_arr: [u8; LEN] = [0; LEN];
+        let mut i: usize = 0;
+        while (CXP[channel].downconn_debug_out_dout_valid_read)() == 1 {
+            pak_arr[i] = (CXP[channel].downconn_debug_out_dout_pak_read)();
+            k_arr[i] = (CXP[channel].downconn_debug_out_kout_pak_read)();
+            // println!("received {:#04X}", pak_arr[i]);
+            (CXP[channel].downconn_debug_out_inc_write)(1);
+            i += 1;
+            if i == LEN {
+                break;
+            }
+        }
+        cxp_proto::print_packetu32(&pak_arr, &k_arr);
+    }
+}
+
+pub fn setup(timer: &mut GlobalTimer) {
+    // TODO: do a for loop for channel?
+    let channel: usize = 0;
+    unsafe {
+        info!("turning on pmc loopback mode...");
+        (CXP[channel].downconn_loopback_mode_write)(0b010); // Near-End PMA Loopback
+
+        // QPLL setup
+        csr::cxp_phys::downconn_qpll_reset_write(1);
+        info!("waiting for QPLL/CPLL to lock...");
+        while csr::cxp_phys::downconn_qpll_locked_read() != 1 {}
+        info!("QPLL locked");
+
+        // tx/rx setup
+        (CXP[channel].downconn_tx_start_init_write)(1);
+        (CXP[channel].downconn_rx_start_init_write)(1);
+
+        info!("waiting for tx & rx setup...");
+        timer.delay_us(50_000);
+        info!(
+            "tx_phaligndone = {} | rx_phaligndone = {}",
+            (CXP[channel].downconn_txinit_phaligndone_read)(),
+            (CXP[channel].downconn_rxinit_phaligndone_read)(),
+        );
+    }
+
+    cxp_gtx::change_linerate(channel, timer, CXP_SPEED::CXP_1);
+}
+
+pub mod cxp_gtx {
+    use super::*;
+
+    struct CdrConfig {
+        pub cfg_reg0: u16, // addr = 0xA8
+        pub cfg_reg1: u16, // addr = 0xA9
+        pub cfg_reg2: u16, // addr = 0xAA
+        pub cfg_reg3: u16, // addr = 0xAB
+        pub cfg_reg4: u16, // addr = 0xAC
+    }
+
+    pub fn change_linerate(channel: usize, timer: &mut GlobalTimer, speed: CXP_SPEED) {
+        info!("Changing datarate to {:?}", speed);
+        // DEBUG: DRP pll for TXUSRCLK = freq(linerate)/20
+        let settings = txusrclk::get_txusrclk_config(speed);
+        txusrclk::setup(channel, timer, settings);
+
+        change_qpll_fb_divider(speed);
+        change_gtx_divider(channel, speed);
+        change_cdr_cfg(channel, speed);
+
+        unsafe {
+            csr::cxp_phys::downconn_qpll_reset_write(1);
+            info!("waiting for QPLL/CPLL to lock...");
+            while csr::cxp_phys::downconn_qpll_locked_read() != 1 {}
+            info!("QPLL locked");
+        }
+
+        unsafe {
+            (CXP[channel].downconn_tx_restart_write)(1);
+            (CXP[channel].downconn_rx_restart_write)(1);
+        }
+    }
+
+    fn change_qpll_fb_divider(speed: CXP_SPEED) {
+        let qpll_div_reg = match speed {
+            CXP_SPEED::CXP_1 | CXP_SPEED::CXP_2 | CXP_SPEED::CXP_5 | CXP_SPEED::CXP_10 => 0x0120, // FB_Divider = 80
+            CXP_SPEED::CXP_3 | CXP_SPEED::CXP_6 | CXP_SPEED::CXP_12 => 0x0170,                    // FB_Divider = 100
+        };
+
+        println!("0x36 = {:#06x}", qpll_read(0x36));
+        qpll_write(0x36, qpll_div_reg);
+        println!("0x36 = {:#06x}", qpll_read(0x36));
+    }
+
+    fn change_gtx_divider(channel: usize, speed: CXP_SPEED) {
+        let div_reg = match speed {
+            CXP_SPEED::CXP_1 => 0x33,                      // RXOUT_DIV = 8
+            CXP_SPEED::CXP_2 | CXP_SPEED::CXP_3 => 0x22,   // RXOUT_DIV = 4
+            CXP_SPEED::CXP_5 | CXP_SPEED::CXP_6 => 0x11,   // RXOUT_DIV = 2
+            CXP_SPEED::CXP_10 | CXP_SPEED::CXP_12 => 0x00, // RXOUT_DIV = 1
+        };
+
+        println!("0x88 = {:#06x}", gtx_read(channel, 0x88));
+        gtx_write(channel, 0x88, div_reg);
+        println!("0x88 = {:#06x}", gtx_read(channel, 0x88));
+    }
+
+    fn change_cdr_cfg(channel: usize, speed: CXP_SPEED) {
+        let cdr_cfg = match speed {
+            // when RXOUT_DIV = 8
+            CXP_SPEED::CXP_1 => {
+                CdrConfig {
+                    cfg_reg0: 0x0020, //0x0A8
+                    cfg_reg1: 0x1008, //0x0A9
+                    cfg_reg2: 0x23FF, //0x0AA
+                    cfg_reg3: 0x0000, //0x0AB
+                    cfg_reg4: 0x0003, //0x0AC
+                }
+            }
+            // when RXOUT_DIV = 4
+            CXP_SPEED::CXP_2 | CXP_SPEED::CXP_5 => {
+                CdrConfig {
+                    cfg_reg0: 0x0020, //0x0A8
+                    cfg_reg1: 0x1010, //0x0A9
+                    cfg_reg2: 0x23FF, //0x0AA
+                    cfg_reg3: 0x0000, //0x0AB
+                    cfg_reg4: 0x0003, //0x0AC
+                }
+            }
+            // when RXOUT_DIV= 2
+            CXP_SPEED::CXP_3 | CXP_SPEED::CXP_6 => {
+                CdrConfig {
+                    cfg_reg0: 0x0020, //0x0A8
+                    cfg_reg1: 0x1020, //0x0A9
+                    cfg_reg2: 0x23FF, //0x0AA
+                    cfg_reg3: 0x0000, //0x0AB
+                    cfg_reg4: 0x0003, //0x0AC
+                }
+            }
+            // when RXOUT_DIV= 1
+            CXP_SPEED::CXP_10 | CXP_SPEED::CXP_12 => {
+                CdrConfig {
+                    cfg_reg0: 0x0020, //0x0A8
+                    cfg_reg1: 0x1040, //0x0A9
+                    cfg_reg2: 0x23FF, //0x0AA
+                    cfg_reg3: 0x0000, //0x0AB
+                    cfg_reg4: 0x000B, //0x0AC
+                }
+            }
+        };
+
+        gtx_write(channel, 0x0A8, cdr_cfg.cfg_reg0);
+        gtx_write(channel, 0x0A9, cdr_cfg.cfg_reg1);
+        gtx_write(channel, 0x0AA, cdr_cfg.cfg_reg2);
+        gtx_write(channel, 0x0AB, cdr_cfg.cfg_reg3);
+        gtx_write(channel, 0x0AC, cdr_cfg.cfg_reg4);
+    }
+
+    #[allow(dead_code)]
+    fn gtx_read(channel: usize, address: u16) -> u16 {
+        unsafe {
+            (CXP[channel].downconn_gtx_daddr_write)(address);
+            (CXP[channel].downconn_gtx_dread_write)(1);
+            while (CXP[channel].downconn_gtx_dready_read)() != 1 {}
+            (CXP[channel].downconn_gtx_dout_read)()
+        }
+    }
+
+    fn gtx_write(channel: usize, address: u16, value: u16) {
+        unsafe {
+            (CXP[channel].downconn_gtx_daddr_write)(address);
+            (CXP[channel].downconn_gtx_din_write)(value);
+            (CXP[channel].downconn_gtx_din_stb_write)(1);
+            while (CXP[channel].downconn_gtx_dready_read)() != 1 {}
+        }
+    }
+
+    #[allow(dead_code)]
+    fn qpll_read(address: u8) -> u16 {
+        unsafe {
+            csr::cxp_phys::downconn_qpll_daddr_write(address);
+            csr::cxp_phys::downconn_qpll_dread_write(1);
+            while csr::cxp_phys::downconn_qpll_dready_read() != 1 {}
+            csr::cxp_phys::downconn_qpll_dout_read()
+        }
+    }
+
+    fn qpll_write(address: u8, value: u16) {
+        unsafe {
+            csr::cxp_phys::downconn_qpll_daddr_write(address);
+            csr::cxp_phys::downconn_qpll_din_write(value);
+            csr::cxp_phys::downconn_qpll_din_stb_write(1);
+            while csr::cxp_phys::downconn_qpll_dready_read() != 1 {}
+        }
+    }
+}
+
+pub mod txusrclk {
+    use super::*;
+
+    pub struct PLLSetting {
+        pub clkout0_reg1: u16,  //0x08
+        pub clkout0_reg2: u16,  //0x09
+        pub clkfbout_reg1: u16, //0x14
+        pub clkfbout_reg2: u16, //0x15
+        pub div_reg: u16,       //0x16
+        pub lock_reg1: u16,     //0x18
+        pub lock_reg2: u16,     //0x19
+        pub lock_reg3: u16,     //0x1A
+        pub power_reg: u16,     //0x28
+        pub filt_reg1: u16,     //0x4E
+        pub filt_reg2: u16,     //0x4F
+    }
+
+    fn one_clock_cycle(channel: usize) {
+        unsafe {
+            (CXP[channel].downconn_pll_dclk_write)(1);
+            (CXP[channel].downconn_pll_dclk_write)(0);
+        }
+    }
+
+    fn set_addr(channel: usize, address: u8) {
+        unsafe {
+            (CXP[channel].downconn_pll_daddr_write)(address);
+        }
+    }
+
+    fn set_data(channel: usize, value: u16) {
+        unsafe {
+            (CXP[channel].downconn_pll_din_write)(value);
+        }
+    }
+
+    fn set_enable(channel: usize, en: bool) {
+        unsafe {
+            let val = if en { 1 } else { 0 };
+            (CXP[channel].downconn_pll_den_write)(val);
+        }
+    }
+
+    fn set_write_enable(channel: usize, en: bool) {
+        unsafe {
+            let val = if en { 1 } else { 0 };
+            (CXP[channel].downconn_pll_dwen_write)(val);
+        }
+    }
+
+    fn get_data(channel: usize) -> u16 {
+        unsafe { (CXP[channel].downconn_pll_dout_read)() }
+    }
+
+    fn drp_ready(channel: usize) -> bool {
+        unsafe { (CXP[channel].downconn_pll_dready_read)() == 1 }
+    }
+
+    #[allow(dead_code)]
+    fn read(channel: usize, address: u8) -> u16 {
+        set_addr(channel, address);
+        set_enable(channel, true);
+        // Set DADDR on the mmcm and assert DEN for one clock cycle
+        one_clock_cycle(channel);
+
+        set_enable(channel, false);
+        while !drp_ready(channel) {
+            // keep the clock signal until data is ready
+            one_clock_cycle(channel);
+        }
+        get_data(channel)
+    }
+
+    fn write(channel: usize, address: u8, value: u16) {
+        set_addr(channel, address);
+        set_data(channel, value);
+        set_write_enable(channel, true);
+        set_enable(channel, true);
+        // Set DADDR, DI on the mmcm and assert DWE, DEN for one clock cycle
+        one_clock_cycle(channel);
+
+        set_write_enable(channel, false);
+        set_enable(channel, false);
+        while !drp_ready(channel) {
+            // keep the clock signal until write is finished
+            one_clock_cycle(channel);
+        }
+    }
+
+    fn reset(channel: usize, rst: bool) {
+        unsafe {
+            let val = if rst { 1 } else { 0 };
+            (CXP[channel].downconn_txpll_reset_write)(val)
+        }
+    }
+
+    pub fn setup(channel: usize, timer: &mut GlobalTimer, settings: PLLSetting) {
+        if false {
+            info!("0x08 = {:#06x}", read(channel, 0x08));
+            info!("0x09 = {:#06x}", read(channel, 0x09));
+            info!("0x14 = {:#06x}", read(channel, 0x14));
+            info!("0x15 = {:#06x}", read(channel, 0x15));
+            info!("0x16 = {:#06x}", read(channel, 0x16));
+            info!("0x18 = {:#06x}", read(channel, 0x18));
+            info!("0x19 = {:#06x}", read(channel, 0x19));
+            info!("0x1A = {:#06x}", read(channel, 0x1A));
+            info!("0x28 = {:#06x}", read(channel, 0x28));
+            info!("0x4E = {:#06x}", read(channel, 0x4E));
+            info!("0x4F = {:#06x}", read(channel, 0x4F));
+        } else {
+            // Based on "DRP State Machine" from XAPP888
+            // hold reset HIGH during pll config
+            reset(channel, true);
+            write(channel, 0x08, settings.clkout0_reg1);
+            write(channel, 0x09, settings.clkout0_reg2);
+            write(channel, 0x14, settings.clkfbout_reg1);
+            write(channel, 0x15, settings.clkfbout_reg2);
+            write(channel, 0x16, settings.div_reg);
+            write(channel, 0x18, settings.lock_reg1);
+            write(channel, 0x19, settings.lock_reg2);
+            write(channel, 0x1A, settings.lock_reg3);
+            write(channel, 0x28, settings.power_reg);
+            write(channel, 0x4E, settings.filt_reg1);
+            write(channel, 0x4F, settings.filt_reg2);
+            reset(channel, false);
+
+            // wait for the pll to lock
+            timer.delay_us(100);
+
+            let locked = unsafe { (CXP[channel].downconn_txpll_locked_read)() == 1 };
+            info!("txusrclk locked = {}", locked);
+        }
+    }
+
+    pub fn get_txusrclk_config(speed: CXP_SPEED) -> PLLSetting {
+        match speed {
+            CXP_SPEED::CXP_1 => {
+                // CLKFBOUT_MULT = 8, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 32
+                // TXUSRCLK=62.5MHz
+                PLLSetting {
+                    clkout0_reg1: 0x1410,  //0x08
+                    clkout0_reg2: 0x0000,  //0x09
+                    clkfbout_reg1: 0x1104, //0x14
+                    clkfbout_reg2: 0x0000, //0x15
+                    div_reg: 0x1041,       //0x16
+                    lock_reg1: 0x03e8,     //0x18
+                    lock_reg2: 0x5801,     //0x19
+                    lock_reg3: 0xdbe9,     //0x1A
+                    power_reg: 0x0000,     //0x28
+                    filt_reg1: 0x9808,     //0x4E
+                    filt_reg2: 0x9100,     //0x4F
+                }
+            }
+            CXP_SPEED::CXP_2 => {
+                // CLKFBOUT_MULT = 8, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 16
+                // TXUSRCLK=62.5MHz
+                PLLSetting {
+                    clkout0_reg1: 0x1208,  //0x08
+                    clkout0_reg2: 0x0000,  //0x09
+                    clkfbout_reg1: 0x1104, //0x14
+                    clkfbout_reg2: 0x0000, //0x15
+                    div_reg: 0x1041,       //0x16
+                    lock_reg1: 0x03e8,     //0x18
+                    lock_reg2: 0x5801,     //0x19
+                    lock_reg3: 0xdbe9,     //0x1A
+                    power_reg: 0x0000,     //0x28
+                    filt_reg1: 0x9808,     //0x4E
+                    filt_reg2: 0x9100,     //0x4F
+                }
+            }
+            CXP_SPEED::CXP_3 => {
+                // CLKFBOUT_MULT = 10, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 16
+                // TXUSRCLK=78.125MHz
+                PLLSetting {
+                    clkout0_reg1: 0x1208,  //0x08
+                    clkout0_reg2: 0x0000,  //0x09
+                    clkfbout_reg1: 0x1145, //0x14
+                    clkfbout_reg2: 0x0000, //0x15
+                    div_reg: 0x1041,       //0x16
+                    lock_reg1: 0x03e8,     //0x18
+                    lock_reg2: 0x7001,     //0x19
+                    lock_reg3: 0xf3e9,     //0x1A
+                    power_reg: 0x0000,     //0x28
+                    filt_reg1: 0x9908,     //0x4E
+                    filt_reg2: 0x1900,     //0x4F
+                }
+            }
+            CXP_SPEED::CXP_5 => {
+                // CLKFBOUT_MULT = 8, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 8
+                // TXUSRCLK=125MHz
+                PLLSetting {
+                    clkout0_reg1: 0x1104,  //0x08
+                    clkout0_reg2: 0x0000,  //0x09
+                    clkfbout_reg1: 0x1104, //0x14
+                    clkfbout_reg2: 0x0000, //0x15
+                    div_reg: 0x1041,       //0x16
+                    lock_reg1: 0x03e8,     //0x18
+                    lock_reg2: 0x5801,     //0x19
+                    lock_reg3: 0xdbe9,     //0x1A
+                    power_reg: 0x0000,     //0x28
+                    filt_reg1: 0x9808,     //0x4E
+                    filt_reg2: 0x9100,     //0x4F
+                }
+            }
+            CXP_SPEED::CXP_6 => {
+                // CLKFBOUT_MULT = 10, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 8
+                // TXUSRCLK=156.25MHz
+                PLLSetting {
+                    clkout0_reg1: 0x1104,  //0x08
+                    clkout0_reg2: 0x0000,  //0x09
+                    clkfbout_reg1: 0x1145, //0x14
+                    clkfbout_reg2: 0x0000, //0x15
+                    div_reg: 0x1041,       //0x16
+                    lock_reg1: 0x03e8,     //0x18
+                    lock_reg2: 0x7001,     //0x19
+                    lock_reg3: 0xf3e9,     //0x1A
+                    power_reg: 0x0000,     //0x28
+                    filt_reg1: 0x9908,     //0x4E
+                    filt_reg2: 0x1900,     //0x4F
+                }
+            }
+            CXP_SPEED::CXP_10 => {
+                // CLKFBOUT_MULT = 8, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 4
+                // TXUSRCLK=250MHz
+                PLLSetting {
+                    clkout0_reg1: 0x1082,  //0x08
+                    clkout0_reg2: 0x0000,  //0x09
+                    clkfbout_reg1: 0x1104, //0x14
+                    clkfbout_reg2: 0x0000, //0x15
+                    div_reg: 0x1041,       //0x16
+                    lock_reg1: 0x03e8,     //0x18
+                    lock_reg2: 0x5801,     //0x19
+                    lock_reg3: 0xdbe9,     //0x1A
+                    power_reg: 0x0000,     //0x28
+                    filt_reg1: 0x9808,     //0x4E
+                    filt_reg2: 0x9100,     //0x4F
+                }
+            }
+            CXP_SPEED::CXP_12 => {
+                // CLKFBOUT_MULT = 10, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 4
+                // TXUSRCLK=312.5MHz
+                PLLSetting {
+                    clkout0_reg1: 0x1082,  //0x08
+                    clkout0_reg2: 0x0000,  //0x09
+                    clkfbout_reg1: 0x1145, //0x14
+                    clkfbout_reg2: 0x0000, //0x15
+                    div_reg: 0x1041,       //0x16
+                    lock_reg1: 0x03e8,     //0x18
+                    lock_reg2: 0x7001,     //0x19
+                    lock_reg3: 0xf3e9,     //0x1A
+                    power_reg: 0x0000,     //0x28
+                    filt_reg1: 0x9908,     //0x4E
+                    filt_reg2: 0x1900,     //0x4F
+                }
+            }
+        }
+    }
+}

src/libboard_artiq/src/cxp_proto.rs

@@ -0,0 +1,267 @@
+use core::slice;
+
+use core_io::{Error as IoError, Write};
+use crc::crc32;
+use io::Cursor;
+use libboard_zynq::println;
+
+// TODO: fix the import
+use crate::{mem::mem::{CXP_LOOPBACK_MEM, CXP_RX_MEM, CXP_TX_MEM},
+            pl::csr::CXP};
+
+const MAX_PACKET: usize = 128;
+const DATA_MAXSIZE: usize = /*max size*/MAX_PACKET - /*Tag*/4 - /*Op code & length*/4 - /*addr*/4 - /*CRC*/4 ;
+const MEM_LEN: usize = 0x200;
+
+#[derive(Debug)]
+pub enum Error {
+    BufferError,
+    LinkDown,
+    UnknownPacket(u8),
+}
+
+impl From<IoError> for Error {
+    fn from(_: IoError) -> Error {
+        Error::BufferError
+    }
+}
+
+pub enum Packet {
+    CtrlRead {
+        addr: u32,
+        length: u8,
+    },
+    CtrlWrite {
+        addr: u32,
+        length: u8,
+        data: [u8; DATA_MAXSIZE],
+    }, // max register size is 8 bytes
+    CtrlReadWithTag {
+        tag: u8,
+        addr: u32,
+        length: u8,
+    },
+    CtrlWriteWithTag {
+        tag: u8,
+        addr: u32,
+        length: u8,
+        data: [u8; DATA_MAXSIZE],
+    }, // max register size is 8 bytes
+    EventAck {
+        packet_tag: u8,
+    },
+    TestPacket,
+}
+
+impl Packet {
+    pub fn write_to(&self, writer: &mut Cursor<&mut [u8]>) -> Result<(), Error> {
+        // CoaXpress use big endian
+        match *self {
+            Packet::CtrlRead { addr, length } => {
+                writer.write(&[0x02; 4])?;
+                writer.write(&[0x00, 0x00, 0x00, length])?;
+                writer.write(&addr.to_be_bytes())?;
+            }
+            Packet::CtrlWrite { addr, length, data } => {
+                writer.write(&[0x02; 4])?;
+                writer.write(&[0x01, 0x00, 0x00, length])?;
+                writer.write(&addr.to_be_bytes())?;
+                writer.write(&data[0..length as usize])?;
+            }
+            Packet::CtrlReadWithTag { tag, addr, length } => {
+                writer.write(&[0x05; 4])?;
+                writer.write(&[tag; 4])?;
+                writer.write(&[0x00, 0x00, 0x00, length])?;
+                writer.write(&addr.to_be_bytes())?;
+            }
+            Packet::CtrlWriteWithTag {
+                tag,
+                addr,
+                length,
+                data,
+            } => {
+                writer.write(&[0x05; 4])?;
+                writer.write(&[tag; 4])?;
+                writer.write(&[0x01, 0x00, 0x00, length])?;
+                writer.write(&addr.to_be_bytes())?;
+                writer.write(&data[0..length as usize])?;
+            }
+            Packet::EventAck { packet_tag } => {
+                writer.write(&[0x08; 4])?;
+                writer.write(&[packet_tag; 4])?;
+            }
+            _ => {}
+        }
+        // Section 9.2.2.2 (CXP-001-2021)
+        // Only Control packet need CRC32 appended in the end of the packet
+        // CoaXpress use the polynomial of IEEE-802.3 (Ethernet) CRC but the checksum calculation is different
+        // Also, the calculation does not include the first 4 bytes of packet_type
+        match *self {
+            Packet::CtrlRead { .. }
+            | Packet::CtrlWrite { .. }
+            | Packet::CtrlReadWithTag { .. }
+            | Packet::CtrlWriteWithTag { .. } => {
+                let checksum = crc32::checksum_ieee(&writer.get_ref()[4..writer.position()]);
+                writer.write(&(!checksum).to_le_bytes())?;
+            }
+            _ => {}
+        }
+        Ok(())
+    }
+}
+
+pub fn receive(channel: usize) -> Result<(), Error> {
+    unsafe {
+        // let ptr = CXP_LOOPBACK_MEM[0].base as *mut u32;
+        let ptr = CXP_RX_MEM[0].base as *mut u32;
+        // let mut reader = Cursor::new(slice::from_raw_parts_mut(ptr as *mut u8, MEM_LEN));
+
+        print_packet(slice::from_raw_parts_mut(ptr as *mut u8, MEM_LEN));
+    }
+    Ok(())
+}
+
+pub fn send(channel: usize, packet: &Packet) -> Result<(), Error> {
+    if unsafe { (CXP[channel].upconn_tx_enable_read)() } == 0 {
+        Err(Error::LinkDown)?
+    }
+
+    match *packet {
+        Packet::TestPacket => send_test_packet(channel),
+        _ => send_data_packet(channel, packet),
+    }
+}
+
+fn send_data_packet(channel: usize, packet: &Packet) -> Result<(), Error> {
+    unsafe {
+        // TODO: put this in mem group
+        while (CXP[channel].upconn_command_tx_read)() == 1 {}
+        let ptr = CXP_TX_MEM[0].base as *mut u32;
+        let mut writer = Cursor::new(slice::from_raw_parts_mut(ptr as *mut u8, MEM_LEN));
+
+        packet.write_to(&mut writer)?;
+
+        (CXP[channel].upconn_command_tx_word_len_write)(writer.position() as u8 / 4);
+        (CXP[channel].upconn_command_tx_write)(1);
+    }
+
+    Ok(())
+}
+
+fn send_test_packet(channel: usize) -> Result<(), Error> {
+    unsafe {
+        while (CXP[channel].upconn_testseq_tx_read)() == 1 {}
+        (CXP[channel].upconn_tx_testmode_en_write)(1);
+        (CXP[channel].upconn_testseq_tx_write)(1);
+
+        // wait till all test packet is out before switching back
+        while (CXP[channel].upconn_testseq_tx_read)() == 1 {}
+        (CXP[channel].upconn_tx_testmode_en_write)(0);
+    }
+    Ok(())
+}
+
+pub fn write_u32(channel: usize, addr: u32, data: u32) -> Result<(), Error> {
+    let mut data_slice: [u8; DATA_MAXSIZE] = [0; DATA_MAXSIZE];
+    data_slice[..4].clone_from_slice(&data.to_be_bytes());
+    send(
+        channel,
+        &Packet::CtrlWrite {
+            addr,
+            length: 4,
+            data: data_slice,
+        },
+    )?;
+
+    Ok(())
+}
+
+pub fn read_u32(channel: usize, addr: u32) -> Result<(), Error> {
+    send(channel, &Packet::CtrlRead { addr, length: 4 })?;
+
+    Ok(())
+}
+
+pub fn write_u64(channel: usize, addr: u32, data: u64) -> Result<(), Error> {
+    let mut data_slice: [u8; DATA_MAXSIZE] = [0; DATA_MAXSIZE];
+    data_slice[..8].clone_from_slice(&data.to_be_bytes());
+    send(
+        channel,
+        &Packet::CtrlWrite {
+            addr,
+            length: 8,
+            data: data_slice,
+        },
+    )?;
+
+    Ok(())
+}
+
+// DEBUG: use only
+pub fn print_packet(pak: &[u8]) {
+    println!("pak = [");
+    for i in 0..(pak.len() / 4) {
+        println!(
+            "{:#03}     {:#04X} {:#04X} {:#04X} {:#04X},",
+            i + 1,
+            pak[i * 4],
+            pak[i * 4 + 1],
+            pak[i * 4 + 2],
+            pak[i * 4 + 3]
+        )
+    }
+    println!("]");
+    println!("============================================");
+}
+
+pub fn print_packetu32(pak: &[u32], k: &[u8]) {
+    println!("pak = [");
+    for i in 0..(pak.len()) {
+        let data: [u8; 4] = pak[i].to_le_bytes();
+        println!(
+            "{:#03}     {:#04X} {:#04X} {:#04X} {:#04X} | K {:04b},",
+            i + 1,
+            data[0],
+            data[1],
+            data[2],
+            data[3],
+            k[i],
+        )
+    }
+    println!("]");
+    println!("============================================");
+}
+
+pub fn downconn_debug_send(channel: usize, packet: &Packet) -> Result<(), Error> {
+    unsafe {
+        // TODO: put this in mem group
+        while (CXP[channel].downconn_command_tx_read)() == 1 {}
+        let ptr = CXP_LOOPBACK_MEM[0].base as *mut u32;
+        let mut writer = Cursor::new(slice::from_raw_parts_mut(ptr as *mut u8, MEM_LEN));
+
+        packet.write_to(&mut writer)?;
+
+        (CXP[channel].downconn_command_tx_word_len_write)(writer.position() as u8 / 4);
+        (CXP[channel].downconn_command_tx_write)(1);
+    }
+
+    Ok(())
+}
+
+pub fn downconn_debug_send_trig_ack(channel: usize) {
+    unsafe {
+        (CXP[channel].downconn_ack_write)(1);
+    }
+}
+
+pub fn downconn_send_test_packet(channel: usize) {
+    unsafe {
+        while (CXP[channel].downconn_testseq_tx_read)() == 1 {}
+        (CXP[channel].downconn_mux_sel_write)(1);
+        (CXP[channel].downconn_testseq_tx_write)(1);
+
+        // wait till all test packet is out before switching back
+        while (CXP[channel].downconn_testseq_tx_read)() == 1 {}
+        (CXP[channel].downconn_mux_sel_write)(0);
+    }
+}

src/libboard_artiq/src/cxp_upconn.rs

@@ -0,0 +1,48 @@
+use embedded_hal::prelude::_embedded_hal_blocking_delay_DelayUs;
+use libboard_zynq::timer::GlobalTimer;
+
+pub use crate::cxp_proto;
+use crate::pl::{csr, csr::CXP};
+
+pub fn tx_test(channel: usize, timer: &mut GlobalTimer) {
+    const LEN: usize = 4 * 30;
+    let mut pak_arr: [u8; LEN] = [0; LEN];
+
+    unsafe {
+        (CXP[channel].upconn_clk_reset_write)(1);
+        // CXP[channel].upconn_bitrate2x_enable_write(1);
+        (CXP[channel].upconn_clk_reset_write)(0);
+
+        (CXP[channel].upconn_tx_enable_write)(1);
+        timer.delay_us(2); // send one word
+        cxp_proto::read_u32(channel, 0x00).expect("Cannot Write CoaXpress Register");
+        // cxp_proto::write_u64(channel, 0x00, 0x01);
+        // cxp_proto::send(channel, &cxp_proto::Packet::EventAck { packet_tag: 0x04 }).expect("Cannot send CoaXpress packet");
+        // cxp_proto::send(channel, &cxp_proto::Packet::TestPacket).expect("Cannot send CoaXpress packet");
+
+        timer.delay_us(2);
+        // DEBUG: Trigger packet
+        (CXP[channel].upconn_trig_delay_write)(0x86);
+        (CXP[channel].upconn_linktrigger_write)(0x00);
+        (CXP[channel].upconn_trig_stb_write)(1); // send trig
+
+        // DEBUG: Trigger ACK packet
+        // CXP[channel].upconn_ack_write(1);
+
+        timer.delay_us(20);
+        (CXP[channel].upconn_tx_enable_write)(0);
+
+        // Collect data
+        let mut i: usize = 0;
+        while csr::cxp_phys::upconn_tx0_debug_buf_dout_valid_read() == 1 {
+            pak_arr[i] = csr::cxp_phys::upconn_tx0_debug_buf_dout_pak_read();
+            csr::cxp_phys::upconn_tx0_debug_buf_inc_write(1);
+            i += 1;
+            if i == LEN {
+                break;
+            }
+        }
+
+        cxp_proto::print_packet(&pak_arr);
+    }
+}

src/libboard_artiq/src/lib.rs

@@ -25,7 +25,7 @@ pub mod fiq;
 #[cfg(feature = "target_kasli_soc")]
 pub mod io_expander;
 pub mod logger;
-#[cfg(has_drtio)]
+#[cfg(any(has_drtio, has_cxp_phys))]
 #[rustfmt::skip]
 #[path = "../../../build/mem.rs"]
 pub mod mem;
@@ -42,6 +42,13 @@ pub mod si5324;
 pub mod si549;
 use core::{cmp, str};
 
+#[cfg(has_cxp_phys)]
+pub mod cxp_downconn;
+#[cfg(has_cxp_phys)]
+pub mod cxp_upconn;
+
+pub mod cxp_proto;
+
 pub fn identifier_read(buf: &mut [u8]) -> &str {
     unsafe {
         pl::csr::identifier::address_write(0);

src/runtime/src/main.rs

@@ -17,7 +17,7 @@ use libasync::task;
 use libboard_artiq::drtio_eem;
 #[cfg(feature = "target_kasli_soc")]
 use libboard_artiq::io_expander;
-use libboard_artiq::{identifier_read, logger, pl};
+use libboard_artiq::{cxp_downconn, cxp_proto, cxp_upconn, identifier_read, logger, pl};
 use libboard_zynq::{gic, mpcore, timer::GlobalTimer};
 use libconfig::Config;
 use libcortex_a9::l2c::enable_l2_cache;
@@ -150,5 +150,19 @@ pub fn main_core0() {
 
     task::spawn(ksupport::report_async_rtio_errors());
 
+    cxp_downconn::setup(&mut timer);
+    // cxp_downconn::loopback_testing(0, &mut timer, cxp_downconn::CXP_SPEED::CXP_1);
+    // cxp_downconn::loopback_testing(0, &mut timer, cxp_downconn::CXP_SPEED::CXP_2);
+    // cxp_downconn::loopback_testing(0, &mut timer, cxp_downconn::CXP_SPEED::CXP_3);
+    // cxp_downconn::loopback_testing(0, &mut timer, cxp_downconn::CXP_SPEED::CXP_5);
+    // cxp_downconn::loopback_testing(0, &mut timer, cxp_downconn::CXP_SPEED::CXP_6);
+    // cxp_downconn::loopback_testing(0, &mut timer, cxp_downconn::CXP_SPEED::CXP_10);
+    // cxp_downconn::loopback_testing(0, &mut timer, cxp_downconn::CXP_SPEED::CXP_12);
+    loop {
+        use embedded_hal::prelude::_embedded_hal_blocking_delay_DelayUs;
+        cxp_upconn::tx_test(0, &mut timer);
+        timer.delay_us(5_000_000);
+    }
+
     comms::main(timer, cfg);
 }