morgan
/
artiq-zynq
forked from M-Labs/artiq-zynq
1
0
Fork 0
Code Pull Requests Activity

cxp GW: add back cdc fifo

This commit is contained in:
morgan 2024-10-02 17:42:15 +08:00
parent 7b0f94674e
commit da9d43e675
1 changed files with 6 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/gateware/cxp.py
View File

@ -180,7 +180,6 @@ class DownConn_Interface(Module, AutoCSR):
# PHY ---/---> CDC FIFO ---/---> trigger ack ------> packet ------> debug buffer
# checker decoder
#
self.submodules.debug_out = debug_out = RX_Debug_Buffer()
self.submodules.trig_ack_checker = trig_ack_checker = CXP_Trig_Ack_Checker()
self.submodules.packet_decoder = packet_decoder = CXP_Data_Packet_Decode()
@ -221,8 +220,13 @@ class DownConn_Interface(Module, AutoCSR):
]
# DEBUG: remove this cdc fifo
cdc_fifo = stream.AsyncFIFO(word_layout, 512)
self.submodules += ClockDomainsRenamer({"write": "cxp_gtx_rx", "read": "sys"})(cdc_fifo)
self.submodules.debug_out = debug_out = RX_Debug_Buffer()
# TODO: move the rx pipeline to cxp_gtx_rx clockdomain
rx_pipeline = [phy, trig_ack_checker, packet_decoder, debug_out]
rx_pipeline = [phy, cdc_fifo, trig_ack_checker, packet_decoder, debug_out]
for s, d in zip(rx_pipeline, rx_pipeline[1:]):
self.comb += s.source.connect(d.sink)