forked from M-Labs/artiq-zynq
zc706: add todo
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@ -709,6 +709,9 @@ class CXP_FMC():
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cxp_loopback_mem_group = []
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for i, (tx, rx) in enumerate(zip(cxp_phys.upconn.tx_phys, cxp_phys.downconn.rx_phys)):
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cxp_name = "cxp" + str(i)
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# TODO: cdr = ClockDomainsRenamer({"cxp_gtx_rx": "cxp_gtx_rx" + str(i)})
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cxp_interface = cxp.CXP_Interface(tx, rx, debug_sma, pmod_pads)
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setattr(self.submodules, cxp_name, cxp_interface )
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self.csr_devices.append(cxp_name)
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