artiq-zynq

morgan

Author	SHA1	Message	Date
morgan	b471db8567	cxp coredevice driver: init	2024-10-24 10:51:07 +08:00
morgan	4f9f90adbf	main fw: cleanup	2024-10-24 10:51:07 +08:00
morgan	9ec0d58652	zc706 GW: add CXP to rtio_channels zc706: update fn names zc706: use cxp_gtx_rxi clk	2024-10-24 10:51:07 +08:00
morgan	2cb823493f	pipeline GW: fix timing pipeline GW: update linktrig pipeline GW: fix idle KCode error pipeline GW: clenaup pipeline GW: cleanup	2024-10-24 10:51:07 +08:00
morgan	9b9f76a8b8	cxp GW: link upconn reset tgt cxp GW: refactor gtx drp cxp GW: remove reset cxp GW: restart read ptr until gtx is ready cxp GW: add rtlink cxp GW: fix linktrig to use 1 bit only cxp GW: separate CXP into Master & extension	2024-10-24 10:51:07 +08:00
morgan	87c0a27566	upconn fw: update csr	2024-10-24 10:51:07 +08:00
morgan	ba3015bffd	downconn fw: fix compilation error downconn fw: update	2024-10-24 10:51:07 +08:00
morgan	66fa70ef3c	proto fw: update csr	2024-10-24 10:51:07 +08:00
morgan	11b3842a7f	upconn GW: link all phy ctrl tgt upconn GW: rename csr upconn GW: add serdes ouput	2024-10-24 10:50:49 +08:00
morgan	d73cd459f0	downconn GW: connect cxp_gtxi cd downconn GW: clenaup	2024-10-24 10:50:49 +08:00
morgan	392f38ed7e	phys fw: add reset phys fw: change linerate to all channels phys fw: refactor and update csr phys fw: reorder reset csr phys fw: set all gtx channel to be same linerate phys fw: clenaup phys fw: add csr control CH len	2024-10-24 10:50:04 +08:00
morgan	675c535812	api: add cxp api support for CTRL packet	2024-10-17 10:53:54 +08:00
morgan	258fdfc4ba	libboard_artiq: setup libboard_artiq: add cxp_downconn & cxp_upconn libboard_artiq: compile mem with cxp libboard_artiq: add cxp_proto libboard_artiq: add cxp_phys	2024-10-17 10:53:54 +08:00
morgan	4f93e47efa	cxp downconn firmware: packet testing	2024-10-17 10:53:54 +08:00
morgan	55b3bd2dbe	cxp upconn firmware: packet testing	2024-10-17 10:53:54 +08:00
morgan	a3ace6ff0c	cxp protocol: init testing: add packet printing helper function testing: add rx loopback proto FW: use memory buffer for tx and rx proto FW: use byteoder crate to handle endianness proto FW: add event packet reader and writer proto FW: add error correction for 4x char	2024-10-17 10:53:54 +08:00
morgan	0c83810519	Cargo: add byteorder	2024-10-17 10:53:54 +08:00
morgan	9967660b3c	main: add testing	2024-10-17 10:53:54 +08:00
morgan	65e7b770b6	cxp_phys: low speed serial & GTX setup downconn: add QPLL & GTX setup downconn: add DRP to change linerate up to 12.5Gbps downconn testing: add txuserclk config upconn: add low speed serital setup upconn & downconn: add linerate changer	2024-10-17 10:53:54 +08:00
morgan	c1cf0eddfb	zc706: add CXP_DEMO variant zc706: add fmc pads zc706: add constraint to fix comma alignment & setup/hold time issue zc706: add csr & mem group for cxp	2024-10-17 10:53:54 +08:00
morgan	c9bb9ea947	cxp: add PHY and pipeline testing: add loopback tx for rx testing testing: add trigger, trigger ack for testing cxp: add upconn & downconn phy cxp: add upconn & downconn pipeline	2024-10-17 10:53:54 +08:00
morgan	502858e64c	cxp pipeline: packet handling pipeline tx pipeline: add CRC32 inserter tx pipeline: add start & end of packet code inserter tx pipeline: add packet wrapper for start & stop packet indication tx pipeline: add code source for trigger & trigger ack packet tx pipeline: add packet for trigger & trigger ack tx pipeline: add test packet generator tx pipeline: add tx_command_packet for firmware tx command packet: add dma to store control packet rx pipeline: add reciever path rx pipeline: add trig ack checker rx pipeline: add packet decoder decoder: add test packet checher decoder: add packet DMA	2024-10-17 10:53:54 +08:00
morgan	d8b823e851	cxp upconn gw: add low speed serial PHY testing: add debug fifo output b4 encoder cxp upconn: add low speed serial cxp upconn: add reset, tx_busy, tx_enable cxp upconn: add clockgen module for 20.83Mbps & 41.66Mbps using counters cxp upconn: add oserdes using CEInserter	2024-10-17 10:53:54 +08:00
morgan	56d54fd0b1	cxp downconn gw: add gtx up to 12.5Gbps testing: add txusrclk mmcm & loopback mode testing: add debug output testing: send comma in the middle of long packet to maintain lock downconn: don't put IDLE into fifo downconn: add GTX and QPLL support downconn: add DRP for GTX and QPLL to support all CXP linerates GTX: add gtx with mmcm for TXUSRCLK freq requirement GTX: add loopback mode parameter for testing GTX: add gtx with 40bits internal width GTX: use built-in comma aligner GTX: add comma checker to ensure comma is aligner on highest linerate GTX: set QPLL as CLK source for GTX	2024-10-17 10:53:54 +08:00

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24 Commits 63112919a3 ... b471db8567

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24 Commits

63112919a3 ... b471db8567