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artiq-zynq
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pipeline GW: fix timing 

pipeline GW: update linktrig

pipeline GW: fix idle KCode error

pipeline GW: clenaup

pipeline GW: cleanup
This commit is contained in:
morgan 2024-10-18 12:16:55 +08:00
parent 9b9f76a8b8
commit 2cb823493f
1 changed files with 14 additions and 15 deletions
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29
src/gateware/cxp_pipeline.py
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@ -47,7 +47,7 @@ class Packet_Wrapper(Module):
self.sink.ack.eq(0),
self.source.stb.eq(1),
self.source.data.eq(Replicate(KCode["pak_start"], 4)),
self.source.k.eq(0b1111),
self.source.k.eq(Replicate(1, 4)),
If(self.source.ack, NextState("COPY")),
)
@ -63,7 +63,7 @@ class Packet_Wrapper(Module):
self.sink.ack.eq(0),
self.source.stb.eq(1),
self.source.data.eq(Replicate(KCode["pak_end"], 4)),
self.source.k.eq(0b1111),
self.source.k.eq(Replicate(1, 4)),
self.source.eop.eq(1),
If(self.source.ack, NextState("IDLE")),
)
@ -72,7 +72,7 @@ class TX_Trigger(Module):
def __init__(self):
self.stb = Signal()
self.delay = Signal(char_width)
self.linktrig_mode = Signal(max=4)
self.linktrig_mode = Signal()
# # #
@ -85,14 +85,14 @@ class TX_Trigger(Module):
trig_packet = [Signal(char_width), Signal(char_width), Signal(char_width), self.delay, self.delay, self.delay]
trig_packet_k = [1, 1, 1, 0, 0, 0]
self.comb += [
If((self.linktrig_mode == 0) | (self.linktrig_mode == 2),
trig_packet[0].eq(KCode["trig_indic_28_2"]),
trig_packet[1].eq(KCode["trig_indic_28_4"]),
trig_packet[2].eq(KCode["trig_indic_28_4"]),
).Else(
If(self.linktrig_mode,
trig_packet[0].eq(KCode["trig_indic_28_4"]),
trig_packet[1].eq(KCode["trig_indic_28_2"]),
trig_packet[2].eq(KCode["trig_indic_28_2"]),
).Else(
trig_packet[0].eq(KCode["trig_indic_28_2"]),
trig_packet[1].eq(KCode["trig_indic_28_4"]),
trig_packet[2].eq(KCode["trig_indic_28_4"]),
),
]
@ -140,7 +140,7 @@ class Idle_Word_Inserter(Module):
self.sink.ack.eq(0),
self.source.stb.eq(1),
self.source.data.eq(Cat(KCode["idle_comma"], KCode["idle_alignment"], KCode["idle_alignment"], C(0xB5, char_width))),
self.source.k.eq(0b1110),
self.source.k.eq(Cat(1, 1, 1, 0)),
If(self.source.ack, NextState("COPY")),
)
@ -166,7 +166,7 @@ class Trigger_ACK_Inserter(Module):
self.sink.ack.eq(0),
self.source.stb.eq(1),
self.source.data.eq(Replicate(KCode["io_ack"], 4)),
self.source.k.eq(0b1111),
self.source.k.eq(Replicate(1, 4)),
If(self.source.ack, NextState("WRITE_ACK1")),
)
@ -174,7 +174,7 @@ class Trigger_ACK_Inserter(Module):
self.sink.ack.eq(0),
self.source.stb.eq(1),
self.source.data.eq(Replicate(C(0x01, char_width), 4)),
self.source.k.eq(0b0000),
self.source.k.eq(Replicate(0, 4)),
If(self.source.ack, NextState("COPY")),
)
@ -240,14 +240,14 @@ class TX_Bootstrap(Module, AutoCSR):
fsm.act("WRITE_TEST_PACKET_TYPE",
self.source.stb.eq(1),
self.source.data.eq(Replicate(C(0x04, char_width), 4)),
self.source.k.eq(0b0000),
self.source.k.eq(Replicate(0, 4)),
If(self.source.ack,NextState("WRITE_TEST_COUNTER"))
)
fsm.act("WRITE_TEST_COUNTER",
self.source.stb.eq(1),
self.source.data.eq(Cat(cnt[:8], cnt[:8]+1, cnt[:8]+2, cnt[:8]+3)),
self.source.k.eq(0b0000),
self.source.k.eq(Cat(0, 0, 0, 0)),
If(self.source.ack,
If(cnt == 0xFFF-3,
self.source.eop.eq(1),
@ -405,6 +405,7 @@ class RX_Bootstrap(Module):
self.comb += [
mem_port.adr[:addr_nbits].eq(addr),
mem_port.adr[addr_nbits:].eq(write_ptr),
mem_port.dat_w.eq(self.sink.data),
]
# For control ack, event packet
@ -416,9 +417,7 @@ class RX_Bootstrap(Module):
NextState("MOVE_BUFFER_PTR"),
).Else(
mem_port.we.eq(1),
mem_port.dat_w.eq(self.sink.data),
NextValue(addr, addr + 1),
If(addr == buffer_depth - 1,
# discard the packet
self.buffer_err.eq(1),