forked from M-Labs/artiq-zynq
cxp GW: link upconn reset tgt
cxp GW: refactor gtx drp cxp GW: remove reset cxp GW: restart read ptr until gtx is ready cxp GW: add rtlink cxp GW: fix linktrig to use 1 bit only cxp GW: separate CXP into Master & extension
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87c0a27566
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9b9f76a8b8
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@ -2,6 +2,8 @@ from migen import *
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from migen.genlib.cdc import MultiReg, PulseSynchronizer
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from misoc.interconnect.csr import *
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from artiq.gateware.rtio import rtlink
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from cxp_downconn import CXP_DownConn_PHYS
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from cxp_upconn import CXP_UpConn_PHYS
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from cxp_pipeline import *
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@ -10,16 +12,14 @@ from cxp_pipeline import *
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class CXP_PHYS(Module, AutoCSR):
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def __init__(self, refclk, upconn_pads, downconn_pads, sys_clk_freq, debug_sma, pmod_pads):
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assert len(upconn_pads) == len(downconn_pads)
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self.submodules.upconn = CXP_UpConn_PHYS(upconn_pads, sys_clk_freq, debug_sma, pmod_pads)
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self.submodules.downconn = CXP_DownConn_PHYS(refclk, downconn_pads, sys_clk_freq, debug_sma, pmod_pads)
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@FullMemoryWE()
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class CXP_Interface(Module, AutoCSR):
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def __init__(self, upconn_phy, downconn_phy, debug_sma, pmod_pads):
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# TODO: add rtio interface io
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self.submodules.upconn = UpConn_Interface(upconn_phy, debug_sma, pmod_pads)
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self.submodules.downconn = DownConn_Interface(downconn_phy, debug_sma, pmod_pads)
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def get_tx_port(self):
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@ -43,6 +43,34 @@ class CXP_Interface(Module, AutoCSR):
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def get_loopback_tx_mem_size(self):
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return self.downconn.bootstrap_loopback.mem.depth*self.downconn.bootstrap_loopback.mem.width // 8
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class CXP_Master(CXP_Interface):
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def __init__(self, upconn_phy, downconn_phy, debug_sma, pmod_pads):
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CXP_Interface.__init__(self, upconn_phy, downconn_phy, debug_sma, pmod_pads)
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nbit_trigdelay = 8
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nbit_linktrig = 1
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self.rtlink = rtlink.Interface(
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rtlink.OInterface(nbit_trigdelay + nbit_linktrig),
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rtlink.IInterface(word_dw, timestamped=False)
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)
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self.sync.rio += [
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If(self.rtlink.o.stb,
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self.upconn.trig.delay.eq(self.rtlink.o.data[nbit_linktrig:]),
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self.upconn.trig.linktrig_mode.eq(self.rtlink.o.data[:nbit_linktrig]),
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),
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self.upconn.trig.stb.eq(self.rtlink.o.stb),
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]
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# DEBUG: out
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self.specials += Instance("OBUF", i_I=self.rtlink.o.stb, o_O=debug_sma.p_tx),
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# self.specials += Instance("OBUF", i_I=self.rtlink.o.stb, o_O=debug_sma.n_rx),
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class CXP_Extension(CXP_Interface):
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def __init__(self, upconn_phy, downconn_phy, debug_sma, pmod_pads):
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CXP_Interface.__init__(self, upconn_phy, downconn_phy, debug_sma, pmod_pads)
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class DownConn_Interface(Module, AutoCSR):
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def __init__(self, phy, debug_sma, pmod_pads):
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self.rx_start_init = CSRStorage()
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@ -95,23 +123,15 @@ class DownConn_Interface(Module, AutoCSR):
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self.comb += gtx.dclk.eq(ClockSignal("sys"))
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self.sync += [
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gtx.den.eq(0),
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gtx.dwen.eq(0),
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If(self.gtx_dread.re,
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gtx.den.eq(1),
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gtx.daddr.eq(self.gtx_daddr.storage),
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).Elif(self.gtx_din_stb.re,
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gtx.den.eq(1),
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gtx.dwen.eq(1),
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gtx.daddr.eq(self.gtx_daddr.storage),
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gtx.din.eq(self.gtx_din.storage),
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),
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gtx.daddr.eq(self.gtx_daddr.storage),
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gtx.den.eq(self.gtx_dread.re | self.gtx_din_stb.re),
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gtx.dwen.eq(self.gtx_din_stb.re),
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gtx.din.eq(self.gtx_din.storage),
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If(gtx.dready,
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self.gtx_dready.w.eq(1),
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self.gtx_dout.status.eq(gtx.dout),
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),
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If(self.gtx_dready.re,
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self.gtx_dready.w.eq(0),
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self.gtx_dready.w.eq(1),
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self.gtx_dout.status.eq(gtx.dout),
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).Elif(self.gtx_dready.re,
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self.gtx_dready.w.eq(0),
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),
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]
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@ -254,7 +274,7 @@ class DownConn_Interface(Module, AutoCSR):
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]
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self.sync += [
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self.pending_packet.w.eq(self.read_ptr.status != bootstrap.write_ptr_sys),
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If(self.rx_restart.re,
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If(~gtx.rx_ready,
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self.read_ptr.status.eq(0),
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).Elif(self.pending_packet.re & self.pending_packet.w,
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self.read_ptr.status.eq(self.read_ptr.status + 1),
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@ -296,7 +316,7 @@ class DownConn_Interface(Module, AutoCSR):
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]
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self.specials += [
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Instance("OBUF", i_I=phy.gtx.cd_cxp_gtx_rx.clk, o_O=debug_sma.p_tx),
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# Instance("OBUF", i_I=phy.gtx.cd_cxp_gtx_rx.clk, o_O=debug_sma.p_tx),
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# Instance("OBUF", i_I=, o_O=debug_sma.p_rx),
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# # pmod 0-7 pin
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Instance("OBUF", i_I=bootstrap.test_err, o_O=pmod_pads[0]),
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@ -312,20 +332,6 @@ class DownConn_Interface(Module, AutoCSR):
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class UpConn_Interface(Module, AutoCSR):
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def __init__(self, phy, debug_sma, pmod_pads):
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self.clk_reset = CSRStorage(reset=1)
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self.bitrate2x_enable = CSRStorage()
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self.tx_enable = CSRStorage()
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self.tx_mux = CSRStorage()
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# # #
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self.sync += [
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phy.bitrate2x_enable.eq(self.bitrate2x_enable.storage),
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phy.tx_enable.eq(self.tx_enable.storage),
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phy.clk_reset.eq(self.clk_reset.re),
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]
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# Transmission Pipeline
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#
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# 32 32 8
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@ -350,13 +356,13 @@ class UpConn_Interface(Module, AutoCSR):
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# # DEBUG: INPUT
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self.trig_stb = CSR()
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self.trig_delay = CSRStorage(8)
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self.linktrigger = CSRStorage(2)
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self.linktrigger = CSRStorage()
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self.sync += [
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trig.stb.eq(self.trig_stb.re),
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trig.delay.eq(self.trig_delay.storage),
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trig.linktrig_mode.eq(self.linktrigger.storage),
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]
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# self.sync += [
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# trig.stb.eq(self.trig_stb.re),
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# trig.delay.eq(self.trig_delay.storage),
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# trig.linktrig_mode.eq(self.linktrigger.storage),
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# ]
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# 1: IO acknowledgment for trigger packet
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