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cxp GW: cleanup

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morgan 2025-01-24 13:35:58 +08:00
parent 6a71b9463d
commit d9e0a6a990
1 changed files with 7 additions and 26 deletions
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33
src/gateware/cxp.py
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@ -75,34 +75,15 @@ class RX_Pipeline(Module, AutoCSR):
self.test_packet_counter = CSRStatus(16)
self.test_counts_reset = CSR()
# For downstream router
self.active = Signal()
# # #
gtx = phy.gtx
self.sync += self.ready.status.eq(gtx.rx_ready)
# # Connect all GTX connections' DRP
# self.gtx_daddr = CSRStorage(9)
# self.gtx_dread = CSR()
# self.gtx_din_stb = CSR()
# self.gtx_din = CSRStorage(16)
# self.gtx_dout = CSRStatus(16)
# self.gtx_dready = CSR()
# self.comb += gtx.dclk.eq(ClockSignal("sys"))
# self.sync += [
# gtx.daddr.eq(self.gtx_daddr.storage),
# gtx.den.eq(self.gtx_dread.re | self.gtx_din_stb.re),
# gtx.dwen.eq(self.gtx_din_stb.re),
# gtx.din.eq(self.gtx_din.storage),
# If(gtx.dready,
# self.gtx_dready.w.eq(1),
# self.gtx_dout.status.eq(gtx.dout),
# ).Elif(self.gtx_dready.re,
# self.gtx_dready.w.eq(0),
# ),
# ]
self.sync += [
self.ready.status.eq(gtx.rx_ready),
self.active.eq(gtx.rx_ready),
]
# Receiver Pipeline WIP
#
@ -487,7 +468,7 @@ class CXP_Frame_Pipeline(Module, AutoCSR):
active_channels_sys = Signal(n_channels)
for i, p in enumerate(pipelines):
# TODO: change this to non csr signal?
self.sync += active_channels_sys[i].eq(p.rx.ready.status)
self.sync += active_channels_sys[i].eq(p.rx.active)
self.specials += MultiReg(active_channels_sys, arbiter.active_channels, odomain="cxp_gtx_rx"),
# DEBUG: