forked from M-Labs/artiq-zynq
cxp fw: update import
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@ -5,9 +5,9 @@ use libboard_zynq::timer::GlobalTimer;
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use log::{info, warn};
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use crate::{cxp_ctrl::{read_u32, read_u64, reset_tag, send_test_packet, write_bytes_no_ack, write_u32, write_u64},
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cxp_phys::{self, CXP_CHANNELS, CXP_SPEED},
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cxp_phys::{change_linerate, CXP_SPEED},
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cxp_proto::Error as ProtoError,
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pl::csr::CXP};
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pl::csr::{CXP, CXP_LEN}};
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// Bootstrap registers address
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const STANDARD: u32 = 0x0000;
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@ -31,6 +31,7 @@ const VERSION_SUPPORTED: u32 = 0x4044;
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const VERSION_USED: u32 = 0x4048;
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// Setup const
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const CXP_CHANNELS: u8 = CXP_LEN as u8;
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// TEST: result
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// Currently, multilane/channel is not working properly in gateware due to buffer overflow issue
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// only single lane @ 0x800 max pak size or dual lane 256 max pak size is working
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@ -110,7 +111,7 @@ fn discover_camera(timer: &mut GlobalTimer) -> Result<(), Error> {
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// 1.25Gbps (CXP_1) and 3.125Gbps (CXP_3) are the discovery rate
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// both linerate need to be checked as camera only support ONE of discovery rates
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for speed in [CXP_SPEED::CXP_1, CXP_SPEED::CXP_3].iter() {
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cxp_phys::change_linerate(*speed);
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change_linerate(*speed);
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// Section 12.1.2 (CXP-001-2021)
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// send ConnectionReset on all channels -> wait 200ms -> scan for active channels
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@ -281,7 +282,7 @@ fn set_operation_linerate(active_channels: u8, with_tag: bool, timer: &mut Globa
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with_tag,
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)?;
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cxp_phys::change_linerate(speed);
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change_linerate(speed);
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timer.delay_ms(200);
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// check no active channels are down after linerate change
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