From d9e0a6a9903a35e843c3ec56c234948459c09c45 Mon Sep 17 00:00:00 2001
From: morgan <mc@m-labs.hk>
Date: Fri, 24 Jan 2025 13:35:58 +0800
Subject: [PATCH] cxp GW: cleanup

---
 src/gateware/cxp.py | 33 +++++++--------------------------
 1 file changed, 7 insertions(+), 26 deletions(-)

diff --git a/src/gateware/cxp.py b/src/gateware/cxp.py
index b682eea..bb3cfaf 100644
--- a/src/gateware/cxp.py
+++ b/src/gateware/cxp.py
@@ -75,34 +75,15 @@ class RX_Pipeline(Module, AutoCSR):
         self.test_packet_counter = CSRStatus(16)
         self.test_counts_reset = CSR()
 
+        # For downstream router
+        self.active = Signal()
         # # #
 
         gtx = phy.gtx
-        self.sync += self.ready.status.eq(gtx.rx_ready)
-
-        # # Connect all GTX connections' DRP
-        # self.gtx_daddr = CSRStorage(9)
-        # self.gtx_dread = CSR()
-        # self.gtx_din_stb = CSR()
-        # self.gtx_din = CSRStorage(16)
-
-        # self.gtx_dout = CSRStatus(16)
-        # self.gtx_dready = CSR()
-
-        # self.comb += gtx.dclk.eq(ClockSignal("sys"))
-        # self.sync += [
-        #     gtx.daddr.eq(self.gtx_daddr.storage),
-        #     gtx.den.eq(self.gtx_dread.re | self.gtx_din_stb.re),
-        #     gtx.dwen.eq(self.gtx_din_stb.re),
-        #     gtx.din.eq(self.gtx_din.storage),
-        #     If(gtx.dready,
-        #         self.gtx_dready.w.eq(1),
-        #         self.gtx_dout.status.eq(gtx.dout),
-        #     ).Elif(self.gtx_dready.re,
-        #         self.gtx_dready.w.eq(0),
-        #     ),
-        # ]
-
+        self.sync += [
+            self.ready.status.eq(gtx.rx_ready),
+            self.active.eq(gtx.rx_ready),
+        ]
 
         # Receiver Pipeline WIP
         # 
@@ -487,7 +468,7 @@ class CXP_Frame_Pipeline(Module, AutoCSR):
         active_channels_sys = Signal(n_channels)
         for i, p in enumerate(pipelines):
             # TODO: change this to non csr signal?
-            self.sync += active_channels_sys[i].eq(p.rx.ready.status)
+            self.sync += active_channels_sys[i].eq(p.rx.active)
         self.specials += MultiReg(active_channels_sys, arbiter.active_channels, odomain="cxp_gtx_rx"),
 
         # DEBUG: