forked from M-Labs/artiq-zynq
cxp GW: add test packet to phy
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@ -1,5 +1,6 @@
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from migen import *
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from misoc.interconnect.csr import *
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from misoc.interconnect import stream
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from cxp_downconn import CXP_DownConn
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from cxp_upconn import CXP_UpConn_PHY
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@ -22,6 +23,8 @@ class UpConn_Interface(Module, AutoCSR):
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self.tx_enable = CSRStorage()
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self.tx_busy = CSRStatus()
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self.tx_testmode_en = CSRStorage()
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# # #
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layout = [("data", 8), ("k", 1)]
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@ -65,4 +68,15 @@ class UpConn_Interface(Module, AutoCSR):
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# 2: All other packets
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# Control is not timing dependent, all the link layer is done in firmware
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self.submodules.command = command = TX_Command_Packet(layout)
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self.comb += command.source.connect(upconn_phy.sinks[2])
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self.submodules.testseq = testseq = TX_Test_Packet(layout)
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self.submodules.mux = mux = stream.Multiplexer(layout, 2)
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self.comb += [
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command.source.connect(mux.sink0),
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testseq.source.connect(mux.sink1),
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mux.sel.eq(self.tx_testmode_en.storage),
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mux.source.connect(upconn_phy.sinks[2])
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]
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