From d9888d7647f4bbf2bfe378734ca9209b03b7cffc Mon Sep 17 00:00:00 2001
From: morgan <mc@m-labs.hk>
Date: Wed, 11 Sep 2024 10:16:47 +0800
Subject: [PATCH] cxp GW: add test packet to phy

---
 src/gateware/cxp.py | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/src/gateware/cxp.py b/src/gateware/cxp.py
index 1a1f599..aa4f608 100644
--- a/src/gateware/cxp.py
+++ b/src/gateware/cxp.py
@@ -1,5 +1,6 @@
 from migen import *
 from misoc.interconnect.csr import *
+from misoc.interconnect import stream
 
 from cxp_downconn import CXP_DownConn
 from cxp_upconn import CXP_UpConn_PHY
@@ -22,6 +23,8 @@ class UpConn_Interface(Module, AutoCSR):
         self.tx_enable = CSRStorage()
         self.tx_busy = CSRStatus()
 
+        self.tx_testmode_en = CSRStorage()
+
         # # #
 
         layout = [("data", 8), ("k", 1)]
@@ -65,4 +68,15 @@ class UpConn_Interface(Module, AutoCSR):
         # 2: All other packets
         # Control is not timing dependent, all the link layer is done in firmware
         self.submodules.command = command = TX_Command_Packet(layout)
-        self.comb += command.source.connect(upconn_phy.sinks[2])
+        self.submodules.testseq = testseq = TX_Test_Packet(layout)
+
+
+        self.submodules.mux = mux = stream.Multiplexer(layout, 2)
+
+        self.comb += [
+            command.source.connect(mux.sink0),
+            testseq.source.connect(mux.sink1),
+            mux.sel.eq(self.tx_testmode_en.storage),
+
+            mux.source.connect(upconn_phy.sinks[2])
+        ]