CXP upconn: add sys reset signal to pll

2024-06-17 16:51:55 +08:00 · 2024-06-17 16:51:55 +08:00 · d36afd6f7b
parent cb1ec7f62a
commit d36afd6f7b
1 changed files with 1 additions and 0 deletions
--- a/src/gateware/cxp_upconn.py
+++ b/src/gateware/cxp_upconn.py
@ -24,6 +24,7 @@ class CXP_UpConn(Module, AutoCSR):
            Instance("PLLE2_ADV",
                p_BANDWIDTH="HIGH",
                o_LOCKED=pll_locked,
+                i_RST=ResetSignal("sys"),
                
                p_CLKIN1_PERIOD=8, # ns
                i_CLKIN1=ClockSignal("sys"),