From d36afd6f7b6f605b001ff0e203e5f8d32920ba7f Mon Sep 17 00:00:00 2001
From: morgan <mc@m-labs.hk>
Date: Mon, 17 Jun 2024 16:51:55 +0800
Subject: [PATCH] CXP upconn: add sys reset signal to pll

---
 src/gateware/cxp_upconn.py | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/gateware/cxp_upconn.py b/src/gateware/cxp_upconn.py
index f3e86d4..e2b08bb 100644
--- a/src/gateware/cxp_upconn.py
+++ b/src/gateware/cxp_upconn.py
@@ -24,6 +24,7 @@ class CXP_UpConn(Module, AutoCSR):
             Instance("PLLE2_ADV",
                 p_BANDWIDTH="HIGH",
                 o_LOCKED=pll_locked,
+                i_RST=ResetSignal("sys"),
                 
                 p_CLKIN1_PERIOD=8, # ns
                 i_CLKIN1=ClockSignal("sys"),