forked from M-Labs/artiq-zynq
zc706 GW: remove unused modules
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ce86e9baf1
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@ -711,30 +711,22 @@ class CXP_FMC():
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for i, phy in enumerate(cxp_phys.phys):
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for i, phy in enumerate(cxp_phys.phys):
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cxp_name = "cxp" + str(i)
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cxp_name = "cxp" + str(i)
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# if i == 0:
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core = cxp.CXP_Core(phy)
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# cxp_interface = cxp.CXP_Master(phy, debug_sma_pad, pmod_pads)
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# # Add rtlink for Master Connection only
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setattr(self.submodules, cxp_name, core)
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# print("CoaXPress at RTIO channel 0x{:06x}".format(len(rtio_channels)))
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# rtio_channels.append(rtio.Channel.from_phy(cxp_interface))
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# else:
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# cxp_interface = cxp.CXP_Extension(phy)
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cxp_interface = cxp.CXP_Core(phy)
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setattr(self.submodules, cxp_name, cxp_interface)
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self.csr_devices.append(cxp_name)
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self.csr_devices.append(cxp_name)
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cxp_csr_group.append(cxp_name)
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cxp_csr_group.append(cxp_name)
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cxp_core_pipelines.append(cxp_interface)
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cxp_core_pipelines.append(core)
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# Add memory group
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# Add memory group
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mem_name = "cxp_" + str(i) + "_mem"
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mem_name = "cxp_" + str(i) + "_mem"
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cxp_mem_group.append(mem_name)
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cxp_mem_group.append(mem_name)
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mem_size = cxp_interface.get_mem_size()
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mem_size = core.get_mem_size()
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# upper half is tx while lower half is rx
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# upper half is tx while lower half is rx
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memory_address = self.axi2csr.register_port(cxp_interface.get_tx_port(), mem_size)
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memory_address = self.axi2csr.register_port(core.get_tx_port(), mem_size)
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self.axi2csr.register_port(cxp_interface.get_rx_port(), mem_size)
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self.axi2csr.register_port(core.get_rx_port(), mem_size)
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self.add_memory_region(mem_name, self.mem_map["csr"] + memory_address, mem_size * 2)
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self.add_memory_region(mem_name, self.mem_map["csr"] + memory_address, mem_size * 2)
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self.add_memory_group("cxp_mem", cxp_mem_group)
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self.add_memory_group("cxp_mem", cxp_mem_group)
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