diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py
index 02a01d8..5e2cba9 100755
--- a/src/gateware/zc706.py
+++ b/src/gateware/zc706.py
@@ -711,30 +711,22 @@ class CXP_FMC():
         for i, phy in enumerate(cxp_phys.phys):
             cxp_name = "cxp" + str(i)
 
-            # if i == 0:
-            #     cxp_interface = cxp.CXP_Master(phy, debug_sma_pad, pmod_pads)
+            core = cxp.CXP_Core(phy)
 
-            #     # Add rtlink for Master Connection only
-            #     print("CoaXPress at RTIO channel 0x{:06x}".format(len(rtio_channels)))
-            #     rtio_channels.append(rtio.Channel.from_phy(cxp_interface))
-            # else:
-            #     cxp_interface = cxp.CXP_Extension(phy)
-            cxp_interface = cxp.CXP_Core(phy)
-
-            setattr(self.submodules, cxp_name, cxp_interface)
+            setattr(self.submodules, cxp_name, core)
             self.csr_devices.append(cxp_name)
             cxp_csr_group.append(cxp_name)
 
-            cxp_core_pipelines.append(cxp_interface)
+            cxp_core_pipelines.append(core)
 
             # Add memory group
 
             mem_name = "cxp_" + str(i) + "_mem"
             cxp_mem_group.append(mem_name)
-            mem_size = cxp_interface.get_mem_size()
+            mem_size = core.get_mem_size()
             # upper half is tx while lower half is rx
-            memory_address = self.axi2csr.register_port(cxp_interface.get_tx_port(), mem_size)
-            self.axi2csr.register_port(cxp_interface.get_rx_port(), mem_size)
+            memory_address = self.axi2csr.register_port(core.get_tx_port(), mem_size)
+            self.axi2csr.register_port(core.get_rx_port(), mem_size)
             self.add_memory_region(mem_name, self.mem_map["csr"] + memory_address, mem_size * 2)
 
         self.add_memory_group("cxp_mem", cxp_mem_group)