forked from M-Labs/artiq-zynq
cxp GW: remove cxp master/extension
This commit is contained in:
parent
eb10bcc530
commit
ce86e9baf1
@ -54,34 +54,6 @@ class CXP_Core(Module, AutoCSR):
|
||||
# TODO: remove this
|
||||
return self.rx.reader.mem.depth*self.downconn.bootstrap.mem.width // 8
|
||||
|
||||
class CXP_Master(CXP_Core):
|
||||
def __init__(self, phy, debug_sma, pmod_pads):
|
||||
CXP_Core.__init__(self, phy)
|
||||
nbit_trigdelay = 8
|
||||
nbit_linktrig = 1
|
||||
|
||||
self.rtlink = rtlink.Interface(
|
||||
rtlink.OInterface(nbit_trigdelay + nbit_linktrig),
|
||||
rtlink.IInterface(word_width, timestamped=False)
|
||||
)
|
||||
|
||||
self.sync.rio += [
|
||||
If(self.rtlink.o.stb,
|
||||
self.tx.trig.delay.eq(self.rtlink.o.data[nbit_linktrig:]),
|
||||
self.tx.trig.linktrig_mode.eq(self.rtlink.o.data[:nbit_linktrig]),
|
||||
),
|
||||
self.tx.trig.stb.eq(self.rtlink.o.stb),
|
||||
]
|
||||
|
||||
# DEBUG: out
|
||||
self.specials += Instance("OBUF", i_I=self.rtlink.o.stb, o_O=debug_sma.p_tx),
|
||||
# self.specials += Instance("OBUF", i_I=self.rtlink.o.stb, o_O=debug_sma.n_rx),
|
||||
|
||||
class CXP_Extension(CXP_Core):
|
||||
def __init__(self, phy):
|
||||
CXP_Core.__init__(self, phy)
|
||||
|
||||
|
||||
class RX_Pipeline(Module, AutoCSR):
|
||||
def __init__(self, phy):
|
||||
self.ready = CSRStatus()
|
||||
|
Loading…
Reference in New Issue
Block a user