morgan
/
artiq-zynq
forked from M-Labs/artiq-zynq
1
0
Fork 0
Code Pull Requests Activity

zc706: add cxp memory map

This commit is contained in:
morgan 2024-09-25 16:58:55 +08:00
parent dbad745b2f
commit a5c0e3b71b
1 changed files with 9 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
src/gateware/zc706.py
View File

@ -698,6 +698,15 @@ class CXP_FMC():
) )
self.csr_devices.append("cxp") self.csr_devices.append("cxp")
# TODO: add memory for tx & rx CXP
memory_name = "cxp_tx"
mem_size = self.cxp.get_mem_size()
memory_address = self.axi2csr.register_port(self.cxp.get_tx_port(), mem_size)
self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, mem_size)
cxp_memory_group = [ memory_name ]
self.add_memory_group("cxp_mem", cxp_memory_group)
# max freq of cxp_gtx_rx = linerate/internal_datawidth = 12.5Gbps/40 = 312.5MHz # max freq of cxp_gtx_rx = linerate/internal_datawidth = 12.5Gbps/40 = 312.5MHz
# zc706 use speed grade 2 which only support up to 10.3125Gbps (4ns) # zc706 use speed grade 2 which only support up to 10.3125Gbps (4ns)
# pushing to 12.5Gbps (3.2ns) will result in Pulse width violation but setup/hold times are met # pushing to 12.5Gbps (3.2ns) will result in Pulse width violation but setup/hold times are met