From a5c0e3b71be89532cafefb638e37f93d86a04ce7 Mon Sep 17 00:00:00 2001 From: morgan Date: Wed, 25 Sep 2024 16:58:55 +0800 Subject: [PATCH] zc706: add cxp memory map --- src/gateware/zc706.py | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index d91c7d7..fe12ec2 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -698,6 +698,15 @@ class CXP_FMC(): ) self.csr_devices.append("cxp") + # TODO: add memory for tx & rx CXP + memory_name = "cxp_tx" + mem_size = self.cxp.get_mem_size() + memory_address = self.axi2csr.register_port(self.cxp.get_tx_port(), mem_size) + self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, mem_size) + cxp_memory_group = [ memory_name ] + self.add_memory_group("cxp_mem", cxp_memory_group) + + # max freq of cxp_gtx_rx = linerate/internal_datawidth = 12.5Gbps/40 = 312.5MHz # zc706 use speed grade 2 which only support up to 10.3125Gbps (4ns) # pushing to 12.5Gbps (3.2ns) will result in Pulse width violation but setup/hold times are met