diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py
index d91c7d7..fe12ec2 100755
--- a/src/gateware/zc706.py
+++ b/src/gateware/zc706.py
@@ -698,6 +698,15 @@ class CXP_FMC():
         )
         self.csr_devices.append("cxp")
 
+        # TODO: add memory for tx & rx CXP
+        memory_name = "cxp_tx"
+        mem_size = self.cxp.get_mem_size()
+        memory_address = self.axi2csr.register_port(self.cxp.get_tx_port(), mem_size)
+        self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, mem_size)
+        cxp_memory_group = [ memory_name ]
+        self.add_memory_group("cxp_mem", cxp_memory_group)
+
+
         # max freq of cxp_gtx_rx = linerate/internal_datawidth = 12.5Gbps/40 = 312.5MHz
         # zc706 use speed grade 2 which only support up to 10.3125Gbps (4ns)
         # pushing to 12.5Gbps (3.2ns) will result in Pulse width violation but setup/hold times are met