morgan
/
artiq-zynq
forked from M-Labs/artiq-zynq
1
0
Fork 0
Code Pull Requests Activity

cxp downconn: refactor QPLl DRP into the module

This commit is contained in:
morgan 2024-08-22 15:43:22 +08:00
parent 1460f5b94b
commit 2dade34119
1 changed files with 30 additions and 53 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

83
src/gateware/cxp_downconn.py
View File

@ -29,8 +29,12 @@ class CXP_DownConn(Module, AutoCSR):
# # # # # #
self.submodules.qpll = qpll = QPLL(refclk, sys_clk_freq) self.submodules.qpll = qpll = QPLL(refclk, sys_clk_freq)
self.sync += [
qpll.reset.eq(self.qpll_reset.re),
self.qpll_locked.status.eq(qpll.lock),
]
# TODO: add gtx slave channel # TODO: add extension gtx connections
# single & master tx_mode can lock with rx in loopback # single & master tx_mode can lock with rx in loopback
self.submodules.gtx = gtx = GTX(self.qpll, pads[0], sys_clk_freq, tx_mode="single", rx_mode="single") self.submodules.gtx = gtx = GTX(self.qpll, pads[0], sys_clk_freq, tx_mode="single", rx_mode="single")
@ -42,9 +46,6 @@ class CXP_DownConn(Module, AutoCSR):
# checkout GTPTXPhaseAlignement for inspiration # checkout GTPTXPhaseAlignement for inspiration
self.sync += [ self.sync += [
# PLL
qpll.reset.eq(self.qpll_reset.re),
self.qpll_locked.status.eq(qpll.lock),
# GTX # GTX
self.txinit_phaligndone.status.eq(gtx.tx_init.Xxphaligndone), self.txinit_phaligndone.status.eq(gtx.tx_init.Xxphaligndone),
self.rxinit_phaligndone.status.eq(gtx.rx_init.Xxphaligndone), self.rxinit_phaligndone.status.eq(gtx.rx_init.Xxphaligndone),
@ -94,39 +95,6 @@ class CXP_DownConn(Module, AutoCSR):
), ),
] ]
# QPLL DRP
self.qpll_daddr = CSRStorage(8)
self.qpll_dread = CSR()
self.qpll_din_stb = CSR()
self.qpll_din = CSRStorage(16)
self.qpll_dout = CSRStatus(16)
self.qpll_dready = CSR()
self.comb += qpll.dclk.eq(ClockSignal("sys"))
self.sync += [
qpll.den.eq(0),
qpll.dwen.eq(0),
If(self.qpll_dread.re,
qpll.den.eq(1),
qpll.daddr.eq(self.qpll_daddr.storage),
).Elif(self.qpll_din_stb.re,
qpll.den.eq(1),
qpll.dwen.eq(1),
qpll.daddr.eq(self.qpll_daddr.storage),
qpll.din.eq(self.qpll_din.storage),
),
If(qpll.dready,
self.qpll_dready.w.eq(1),
self.qpll_dout.status.eq(qpll.dout),
),
If(self.qpll_dready.re,
self.qpll_dready.w.eq(0),
),
]
# DEBUG: txusrclk PLL DRG # DEBUG: txusrclk PLL DRG
self.txpll_reset = CSRStorage() self.txpll_reset = CSRStorage()
@ -224,22 +192,21 @@ class CXP_DownConn(Module, AutoCSR):
] ]
class QPLL(Module): class QPLL(Module, AutoCSR):
def __init__(self, refclk, sys_clk_freq): def __init__(self, refclk, sys_clk_freq):
self.clk = Signal() self.clk = Signal()
self.refclk = Signal() self.refclk = Signal()
self.lock = Signal() self.lock = Signal()
self.reset = Signal() self.reset = Signal()
# Dynamic Reconfiguration Ports self.daddr = CSRStorage(8)
self.daddr = Signal(8) self.dread = CSR()
self.dclk = Signal() self.din_stb = CSR()
self.den = Signal() self.din = CSRStorage(16)
self.dwen = Signal()
self.din = Signal(16) self.dout = CSRStatus(16)
self.dready = CSR()
self.dout = Signal(16)
self.dready = Signal()
# # # # # #
# VCO @ 10GHz, linerate = 1.25Gbps # VCO @ 10GHz, linerate = 1.25Gbps
@ -253,6 +220,7 @@ class QPLL(Module):
fbdiv_real = 80 fbdiv_real = 80
self.tx_usrclk_freq = (sys_clk_freq*fbdiv_real/self.Xxout_div)/40 self.tx_usrclk_freq = (sys_clk_freq*fbdiv_real/self.Xxout_div)/40
dready = Signal()
self.specials += [ self.specials += [
Instance("GTXE2_COMMON", Instance("GTXE2_COMMON",
i_QPLLREFCLKSEL=0b001, i_QPLLREFCLKSEL=0b001,
@ -295,16 +263,25 @@ class QPLL(Module):
i_QPLLRSVD2=0b11111, i_QPLLRSVD2=0b11111,
# Dynamic Reconfiguration Ports # Dynamic Reconfiguration Ports
i_DRPADDR=self.daddr, i_DRPADDR=self.daddr.storage,
i_DRPCLK=self.dclk, i_DRPCLK=ClockSignal("sys"),
i_DRPEN=self.den, i_DRPEN=(self.dread.re | self.din_stb.re),
i_DRPWE=self.dwen, i_DRPWE=self.din_stb.re,
i_DRPDI=self.din, i_DRPDI=self.din.storage,
o_DRPDO=self.dout, o_DRPDO=self.dout.status,
o_DRPRDY=self.dready, o_DRPRDY=dready,
) )
] ]
self.sync += [
If(dready,
self.dready.w.eq(1),
),
If(self.dready.re,
self.dready.w.eq(0),
),
]
# Warning: Xilinx transceivers are LSB first, and comma needs to be flipped # Warning: Xilinx transceivers are LSB first, and comma needs to be flipped
# compared to the usual 8b10b binary representation. # compared to the usual 8b10b binary representation.
class Comma_Checker(Module): class Comma_Checker(Module):