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artiq-zynq
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cxp downconn fw: fix warning and cleanup

This commit is contained in:
morgan 2024-08-22 12:50:50 +08:00
parent 66dee0b812
commit 1460f5b94b
1 changed files with 19 additions and 34 deletions
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53
src/libboard_artiq/src/cxp_downconn.rs
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@ -5,11 +5,6 @@ use log::info;
// use log::info;
use crate::pl::csr;
pub struct CXP_DownConn_Settings {
pub rxdiv: u8,
pub qpll_fbdiv: u8,
}
#[derive(Clone, Copy, Debug)]
#[allow(non_camel_case_types)]
pub enum CXP_SPEED {
@ -24,7 +19,7 @@ pub enum CXP_SPEED {
pub fn loopback_testing(timer: &mut GlobalTimer, speed: CXP_SPEED) {
println!("==============================================================================");
CXP_GTX::change_linerate(timer, speed);
cxp_gtx::change_linerate(timer, speed);
unsafe {
info!("waiting for tx&rx setup...");
@ -42,8 +37,8 @@ pub fn loopback_testing(timer: &mut GlobalTimer, speed: CXP_SPEED) {
while csr::cxp::downconn_rx_ready_read() != 1 {}
info!("rx ready!");
// loop {
for _ in 0..20 {
loop {
// for _ in 0..20 {
// NOTE: raw bits
// let data0 = csr::cxp::downconn_rxdata_0_read();
// let data1 = csr::cxp::downconn_rxdata_1_read();
@ -75,7 +70,7 @@ pub fn loopback_testing(timer: &mut GlobalTimer, speed: CXP_SPEED) {
// timer.delay_us(1_000_000);
// }
// timer.delay_us(1_000_000);
timer.delay_us(1_000_000);
// NOTE: raw bits
// let data0 = csr::cxp::downconn_rxdata_0_read();
// let data1 = csr::cxp::downconn_rxdata_1_read();
@ -134,13 +129,13 @@ pub fn setup(timer: &mut GlobalTimer) {
);
}
CXP_GTX::change_linerate(timer, CXP_SPEED::CXP_1);
cxp_gtx::change_linerate(timer, CXP_SPEED::CXP_1);
}
pub mod CXP_GTX {
pub mod cxp_gtx {
use super::*;
struct RX_CDR_CFG {
struct CdrConfig {
pub cfg_reg0: u16, //0x0A8
pub cfg_reg1: u16, //0x0A9
pub cfg_reg2: u16, //0x0AA
@ -177,9 +172,7 @@ pub mod CXP_GTX {
CXP_SPEED::CXP_3 | CXP_SPEED::CXP_6 | CXP_SPEED::CXP_12 => 0x0170, // FB_Divider = 100
};
println!("0x36 = {:#018b}", qpll_read(0x36));
qpll_write(0x36, qpll_div_reg);
println!("0x36 = {:#018b}", qpll_read(0x36));
let rxout_div = match speed {
CXP_SPEED::CXP_1 => 0b100, // 8
@ -198,7 +191,7 @@ pub mod CXP_GTX {
let cdr_cfg = match speed {
// rxout_div = 8
CXP_SPEED::CXP_1 => {
RX_CDR_CFG {
CdrConfig {
cfg_reg0: 0x0020, //0x0A8
cfg_reg1: 0x1008, //0x0A9
cfg_reg2: 0x23FF, //0x0AA
@ -208,7 +201,7 @@ pub mod CXP_GTX {
}
// rxout_div = 4
CXP_SPEED::CXP_2 | CXP_SPEED::CXP_5 => {
RX_CDR_CFG {
CdrConfig {
cfg_reg0: 0x0020, //0x0A8
cfg_reg1: 0x1010, //0x0A9
cfg_reg2: 0x23FF, //0x0AA
@ -218,7 +211,7 @@ pub mod CXP_GTX {
}
// rxout_div = 2
CXP_SPEED::CXP_3 | CXP_SPEED::CXP_6 => {
RX_CDR_CFG {
CdrConfig {
cfg_reg0: 0x0020, //0x0A8
cfg_reg1: 0x1020, //0x0A9
cfg_reg2: 0x23FF, //0x0AA
@ -226,19 +219,9 @@ pub mod CXP_GTX {
cfg_reg4: 0x0003, //0x0AC
}
}
// // Divided by 1
// CXP_SPEED::CXP_6 => {
// RX_CDR_CFG {
// cfg_reg0: 0x0020, //0x0A8
// cfg_reg1: 0x1040, //0x0A9
// cfg_reg2: 0x23FF, //0x0AA
// cfg_reg3: 0x0000, //0x0AB
// cfg_reg4: 0x0003, //0x0AC
// }
// }
// rxout_div = 1
CXP_SPEED::CXP_10 | CXP_SPEED::CXP_12 => {
RX_CDR_CFG {
CdrConfig {
cfg_reg0: 0x0020, //0x0A8
cfg_reg1: 0x1040, //0x0A9
cfg_reg2: 0x23FF, //0x0AA
@ -255,31 +238,33 @@ pub mod CXP_GTX {
gtx_write(0x0AC, cdr_cfg.cfg_reg4);
}
#[allow(dead_code)]
fn gtx_read(address: u16) -> u16 {
// DEBUG: DRPCLK need to be on for a few cycle before accessing other DRP ports
// DEBUG:
unsafe {
csr::cxp::downconn_gtx_daddr_write(address);
csr::cxp::downconn_gtx_dread_write(1);
while (csr::cxp::downconn_gtx_dready_read() != 1) {}
while csr::cxp::downconn_gtx_dready_read() != 1 {}
csr::cxp::downconn_gtx_dout_read()
}
}
fn gtx_write(address: u16, value: u16) {
// DEBUG: DRPCLK need to be on for a few cycle before accessing other DRP ports
unsafe {
csr::cxp::downconn_gtx_daddr_write(address);
csr::cxp::downconn_gtx_din_write(value);
csr::cxp::downconn_gtx_din_stb_write(1);
while (csr::cxp::downconn_gtx_dready_read() != 1) {}
while csr::cxp::downconn_gtx_dready_read() != 1 {}
}
}
#[allow(dead_code)]
fn qpll_read(address: u8) -> u16 {
// DEBUG:
unsafe {
csr::cxp::downconn_qpll_daddr_write(address);
csr::cxp::downconn_qpll_dread_write(1);
while (csr::cxp::downconn_qpll_dready_read() != 1) {}
while csr::cxp::downconn_qpll_dready_read() != 1 {}
csr::cxp::downconn_qpll_dout_read()
}
}
@ -289,7 +274,7 @@ pub mod CXP_GTX {
csr::cxp::downconn_qpll_daddr_write(address);
csr::cxp::downconn_qpll_din_write(value);
csr::cxp::downconn_qpll_din_stb_write(1);
while (csr::cxp::downconn_qpll_dready_read() != 1) {}
while csr::cxp::downconn_qpll_dready_read() != 1 {}
}
}
}