From 2dade34119147b5383892eedfd74903c5f4242b8 Mon Sep 17 00:00:00 2001
From: morgan <mc@m-labs.hk>
Date: Thu, 22 Aug 2024 15:43:22 +0800
Subject: [PATCH] cxp downconn: refactor QPLl DRP into the module

---
 src/gateware/cxp_downconn.py | 83 +++++++++++++-----------------------
 1 file changed, 30 insertions(+), 53 deletions(-)

diff --git a/src/gateware/cxp_downconn.py b/src/gateware/cxp_downconn.py
index c985feb..638ccfe 100644
--- a/src/gateware/cxp_downconn.py
+++ b/src/gateware/cxp_downconn.py
@@ -29,8 +29,12 @@ class CXP_DownConn(Module, AutoCSR):
         # # #
 
         self.submodules.qpll = qpll = QPLL(refclk, sys_clk_freq)
+        self.sync += [
+            qpll.reset.eq(self.qpll_reset.re),
+            self.qpll_locked.status.eq(qpll.lock),
+        ]
 
-        # TODO: add gtx slave channel
+        # TODO: add extension gtx connections
 
         # single & master tx_mode can lock with rx in loopback 
         self.submodules.gtx = gtx = GTX(self.qpll, pads[0], sys_clk_freq, tx_mode="single", rx_mode="single")
@@ -42,9 +46,6 @@ class CXP_DownConn(Module, AutoCSR):
         # checkout GTPTXPhaseAlignement for inspiration
 
         self.sync += [
-            # PLL
-            qpll.reset.eq(self.qpll_reset.re),
-            self.qpll_locked.status.eq(qpll.lock),
             # GTX
             self.txinit_phaligndone.status.eq(gtx.tx_init.Xxphaligndone),
             self.rxinit_phaligndone.status.eq(gtx.rx_init.Xxphaligndone),
@@ -94,39 +95,6 @@ class CXP_DownConn(Module, AutoCSR):
             ),
         ]
 
-        # QPLL DRP
-
-        self.qpll_daddr = CSRStorage(8)
-        self.qpll_dread = CSR()
-        self.qpll_din_stb = CSR()
-        self.qpll_din = CSRStorage(16)
-
-        self.qpll_dout = CSRStatus(16)
-        self.qpll_dready = CSR()
-
-        self.comb += qpll.dclk.eq(ClockSignal("sys"))
-        self.sync += [
-            qpll.den.eq(0),
-            qpll.dwen.eq(0),
-
-            If(self.qpll_dread.re,
-                qpll.den.eq(1),
-                qpll.daddr.eq(self.qpll_daddr.storage),
-            ).Elif(self.qpll_din_stb.re,
-                qpll.den.eq(1),
-                qpll.dwen.eq(1),
-                qpll.daddr.eq(self.qpll_daddr.storage),
-                qpll.din.eq(self.qpll_din.storage),
-            ),
-            If(qpll.dready,
-               self.qpll_dready.w.eq(1),
-               self.qpll_dout.status.eq(qpll.dout),
-            ),
-            If(self.qpll_dready.re,
-               self.qpll_dready.w.eq(0),
-            ),
-        ]
-
         # DEBUG: txusrclk PLL DRG
         
         self.txpll_reset = CSRStorage()
@@ -224,22 +192,21 @@ class CXP_DownConn(Module, AutoCSR):
         ]
 
 
-class QPLL(Module):
+class QPLL(Module, AutoCSR):
     def __init__(self, refclk, sys_clk_freq):
         self.clk = Signal()
         self.refclk = Signal()
         self.lock = Signal()
         self.reset = Signal()
 
-        # Dynamic Reconfiguration Ports
-        self.daddr = Signal(8)
-        self.dclk = Signal()
-        self.den = Signal()
-        self.dwen = Signal()
-        self.din = Signal(16)
+        self.daddr = CSRStorage(8)
+        self.dread = CSR()
+        self.din_stb = CSR()
+        self.din = CSRStorage(16)
+
+        self.dout = CSRStatus(16)
+        self.dready = CSR()
 
-        self.dout = Signal(16)
-        self.dready = Signal()
         # # #
 
         # VCO @ 10GHz, linerate = 1.25Gbps
@@ -253,6 +220,7 @@ class QPLL(Module):
         fbdiv_real = 80
         self.tx_usrclk_freq = (sys_clk_freq*fbdiv_real/self.Xxout_div)/40
         
+        dready = Signal()
         self.specials += [
             Instance("GTXE2_COMMON",
                 i_QPLLREFCLKSEL=0b001,
@@ -295,16 +263,25 @@ class QPLL(Module):
                 i_QPLLRSVD2=0b11111,
 
                 # Dynamic Reconfiguration Ports
-                i_DRPADDR=self.daddr,
-                i_DRPCLK=self.dclk,
-                i_DRPEN=self.den,
-                i_DRPWE=self.dwen,
-                i_DRPDI=self.din,
-                o_DRPDO=self.dout,
-                o_DRPRDY=self.dready,
+                i_DRPADDR=self.daddr.storage,
+                i_DRPCLK=ClockSignal("sys"),
+                i_DRPEN=(self.dread.re | self.din_stb.re),
+                i_DRPWE=self.din_stb.re,
+                i_DRPDI=self.din.storage,
+                o_DRPDO=self.dout.status,
+                o_DRPRDY=dready,
             )
         ]
 
+        self.sync += [
+            If(dready,
+               self.dready.w.eq(1),
+            ),
+            If(self.dready.re,
+               self.dready.w.eq(0),
+            ),
+        ]
+
 # Warning: Xilinx transceivers are LSB first, and comma needs to be flipped
 # compared to the usual 8b10b binary representation.
 class Comma_Checker(Module):