39724de598
core: Add CodeGenLLVMOptions
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For specifying LLVM options during code generation.
2023-09-12 10:57:04 +08:00
4481d48709
core: Use C-style for loop logic for iterables
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Index increment is now performed at the end of the loop body.
2023-09-06 20:09:38 +08:00
b4983526bd
core: Remove redundant for.cond BB for iterable loops
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Simplifies logic for creating basic blocks.
2023-09-06 20:09:37 +08:00
b4a9616648
core: Add assertion for when range has step of 0
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Aligns with the behavior in Python.
2023-09-06 20:09:36 +08:00
e0de82993f
core: Preserve value of variable shadowed by for loop
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Previously, the final value of the target expression would be one after
the last element of the loop, which does not match Python's behavior.
This commit fixes this problem while also preserving the last assigned
value of the loop beyond the loop, matching Python's behavior.
2023-09-06 20:09:36 +08:00
6805253515
core: Use AST var name for IR name
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Aids debugging IR.
2023-09-06 20:09:36 +08:00
19915bac79
core: Prepend statement type to basic block label names
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Aids debugging IR.
2023-09-06 20:09:36 +08:00
6de0884dc1
core: Use anonymous name for variables if unspecified
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The current default prefix is only derived from the instruction type,
which is not helpful during the comprehension of the IR. Changing to
anonymous names (e.g. %1) helps understand that the variable is only
needed as part of a larger (possibly named) expression.
2023-09-06 14:02:15 +08:00
f1b0e05b3d
core: Rename IR variables
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Because it is unclear which variables are expressions and
subexpressions, all variables which are previously anonymous are named
using (1) the control flow statement if available, (2) the possible name
of the variable as inferred from the variable name in Rust, and (3) the
"addr" prefix to indicate that the values are pointers. These three
strings are joint together using '.', forming "for.i.addr" for instance.
2023-09-06 14:02:15 +08:00
ff23968544
core: Add name parameter to gen_{var_alloc,store_target}
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This allows variables in the IR to be assigned a custom name as opposed
to names with a default prefix.
2023-09-06 11:00:02 +08:00
d37287a33d
Cargo: Update dependencies
2023-09-04 10:43:57 +08:00
aead36f0fd
update dependencies
2023-03-08 15:19:09 +08:00
c1c45373a6
update dependencies
2023-01-12 19:31:03 +08:00
085c6ee738
update dependencies
2022-11-18 16:15:46 +08:00
f66ca02b2d
update Rust dependencies
2022-08-05 16:58:57 +08:00
ebd25af38b
nac3standalone: allow classes without explicit init ( #221 )
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Reviewed-on: M-Labs/nac3#304
Co-authored-by: z78078 <cc@m-labs.hk>
Co-committed-by: z78078 <cc@m-labs.hk>
2022-07-07 10:36:25 +08:00
96b3a3bf5c
work around random segmentation fault ( #275 )
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Reviewed-on: M-Labs/nac3#302
Co-authored-by: z78078 <cc@m-labs.hk>
Co-committed-by: z78078 <cc@m-labs.hk>
2022-07-04 18:06:36 +08:00
a18d095245
nac3core: codegen fix call parameter type error
2022-07-04 14:39:33 +08:00
5d5e9a5e02
nac3core: fix codegen error of inheritance
2022-06-01 17:58:16 +08:00
c4ab2855e5
nac3core: pretty print codegen panic error
2022-05-30 04:09:21 +08:00
ffac37dc48
nac3core: fix exception type in primitive store
2022-05-29 19:14:00 +08:00
76473152e8
nac3core: fix llvm.expect intrinsic name
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this might be one of the causes for the random segfault bug
2022-05-27 04:23:49 +08:00
096f4b03c0
nac3core: fix assignment
2022-05-14 02:30:08 +08:00
a022005183
nac3core: fix broken tests
2022-05-11 03:53:53 +08:00
325ba0a408
nac3core: add debug info
2022-05-11 03:53:53 +08:00
3f327113b2
update dependencies, use upstream inkwell
2022-04-27 15:41:46 +08:00
a321b13bec
fix typos
2022-04-27 11:08:10 +08:00
48cb485b89
nac3core: show outer type info in type error messages
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Reviewed-on: M-Labs/nac3#274
Co-authored-by: ychenfo <yc@m-labs.hk>
Co-committed-by: ychenfo <yc@m-labs.hk>
2022-04-22 15:31:55 +08:00
85f21060e4
update to LLVM 14
2022-04-18 18:47:20 +08:00
1eac111d4c
cleanup
2022-04-18 15:55:37 +08:00
711c3d3303
nac3core: support custom operators
2022-04-18 15:31:56 +08:00
wylited
35b6459c58
nac3core: replace paramter with parameter
2022-04-13 15:42:26 +08:00
e94b25f544
spelling ( #264 )
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Co-authored-by: wylited <ds@m-labs.hk>
Co-committed-by: wylited <ds@m-labs.hk>
2022-04-13 11:32:31 +08:00
1e7abf0268
fix tests
2022-04-12 10:06:41 +08:00
f5a6d29106
update insta snapshots
2022-04-12 09:56:49 +08:00
ca07cb66cd
format typevars consistently
2022-04-12 09:28:17 +08:00
722e3df086
nac3core, artiq: optimize kernel invariant for tuple index
2022-04-11 14:58:40 +08:00
ad9ad22cb8
nac3core: optimize unwrap KernelInvariant
2022-04-11 14:58:35 +08:00
f66f66b3a4
nac3core, artiq: remove unnecessary ptr casts
2022-04-10 01:28:46 +08:00
0e0871bc38
nac3core, artiq: to_basic_value_enum takes an argument indicating the expected type
2022-04-10 01:28:22 +08:00
26187bff0b
nac3core: add missing bound check and negative index handling for list subscription assignment
2022-04-09 04:56:31 +08:00
c29cbf6ddd
nac3core: add bound check for list slice
2022-04-05 18:21:46 +08:00
7443c5ea0f
nac3core: add location information to codegen context
2022-04-05 18:21:46 +08:00
710904f975
nac3core: fix powi with negative integer power
2022-04-04 22:10:56 +08:00
2edeb31d21
nac3core: do not get llvm value too eagerly for kernel invariant
2022-03-31 10:28:16 +08:00
c3156afebd
nac3core: fix broken tests
2022-03-30 04:05:47 +08:00
388c9b7241
nac3core: better check and err msg for default param
2022-03-30 04:05:47 +08:00
6ab73a223c
nac3core/artiq: support default param of option type
2022-03-30 04:05:47 +08:00
a38cc04444
nac3core: assert statement
2022-03-29 06:56:40 +08:00
1f5826d352
fix ternary if ( #250 )
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Use store and load to handle if expression as the blocks might be changed when generating sub-expressions.
Reviewed-on: M-Labs/nac3#250
Co-authored-by: ychenfo <yc@m-labs.hk>
Co-committed-by: ychenfo <yc@m-labs.hk>
2022-03-29 06:54:00 +08:00
