Compare commits

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102 Commits

Author SHA1 Message Date
4c69a080b1 bom: update MFR_PN and descriptions of SMA Cable 2024-02-06 17:11:23 +08:00
c08d3d36b4 Panel: Add Mounting Plates for Fiber Optic Adapters 2024-02-05 14:40:11 +08:00
c7cfa18a99 sch: Add M3 Washer to BOM 2024-01-30 12:06:45 +08:00
43c5afefab sch: correct MFR/PNs for BSS138, TLV9001, TPS54620 2024-01-24 10:35:08 +08:00
0cb1e783c0 flake: cleanup tmpdir management 2023-12-30 11:47:59 +08:00
b5d6ee6035 flake: update dependencies 2023-12-30 11:47:48 +08:00
b802e37bf4 flake: Create TMP dir and use it for $HOME PATH 2023-12-21 16:22:19 +08:00
1a4b4a2484 sch, pcb: Correct opamp input polarity of TEC_VSEN
- +ve IN connects to TEC+
- -ve IN  connects to TEC-
2023-12-19 17:49:15 +08:00
f847cfadb4 sch, pcb: Add 0R to use TEC_VREF to bias TEC_VSEN
- Optional
2023-12-19 17:08:10 +08:00
f3f3e609e5 Update Front Panel Text Markings
- Move the LF MOD and HF MOD text up by 1.5mm
2023-12-18 16:05:12 +08:00
80b9848539 update flake: KiCAD_BOM_Generator 2023-12-18 16:05:12 +08:00
a2cb5ce624 sch, pcb: Add TDAC_VFB. Change 2u2 PMLCAP P/N
- Connect TDAC voltage output through a RC LPF to MCU PC0(ADC123_IN10)
- 2u2 PMLCAP P/N is changed to 16V version instead of 35V for lower cost
2023-12-18 16:05:08 +08:00
7ac52b7a1b PCB: Correct Y169010R0000T9L Footprint
- Add more space between the pin holes and resistor body
2023-12-13 15:33:49 +08:00
901f394ab3 Correct graphical mistakes in LTC3261 symbol
- no functional changes
2023-12-13 12:18:14 +08:00
ef732cf36b sch, pcb: correct polarity of LT3094xMSE C_Set 2023-12-13 11:50:50 +08:00
6cd368a203 sch: Add SMA Jack to Plug Cable to BOM
- Internal SMA cable connecting LD adapter and Front Panel
2023-12-13 11:29:01 +08:00
eaea402d9c Add copper plate to LD Adapter 3D model 2023-12-13 11:29:01 +08:00
9e1f359d78 flake: Generate prod files with flake.nix
- Generate production files with nix build .
2023-12-13 11:29:01 +08:00
a0c1ca1c58 pcb: Update clearance rules for JLCPCB manufacturing
- No layout is changed. Only copper clearance and width are modified.
2023-12-13 11:29:00 +08:00
aa8fd2c5cb sch: Update PN and Comments 2023-12-13 11:29:00 +08:00
6d686d7170 sch: Place Y169010R Power Resistor
- cannot find purchasable PDY10R000F Power Resistor
2023-12-13 11:29:00 +08:00
816e273b7a sch: Add JLCPCB M3 x 8 Screws PN 2023-12-13 11:29:00 +08:00
b0e798a83e sch: Set the mcu 2.54mm Prog HDR to be placed 2023-12-13 11:29:00 +08:00
19a860fbb4 sch: Specify AD5680 MFR_PN to be -1 variant 2023-12-13 11:29:00 +08:00
430a67dda4 pcb: Update Front Panel 3D Model 2023-12-13 11:29:00 +08:00
71f2a39713 Add Front Panel Mechanical Design and Drawings
- Complete the Assembly in FreeCAD
- Add Technical Drawings, Assembly Drawings, 3D model for production
- Update text markings on KiCad
2023-12-13 11:28:56 +08:00
3b7fbdb2be pcb: Update PN and properties of symbols 2023-11-30 16:14:59 +08:00
8b3d5d8e44 sch: Not to include TPs in BOM. Add prod comments
- LTC6655 Vref adds production comments
2023-11-30 16:14:59 +08:00
83bd5e9a03 Front Panel: Relocate markings to diff layers
- Move the markings to different layers for generating prod docs
- Add comments in the drawings pdf
2023-11-30 16:14:55 +08:00
cc64790270 pcb: relocate programming hdrs
- prev locations block Internal SMA cable
2023-11-30 14:55:15 +08:00
56ef8302a7 sch: Correct Front Panel Kit MRF/PN & Value typo 2023-11-30 14:53:01 +08:00
007ba75003 pcb: Add GND and via fencing for Mod_IN signal 2023-11-30 11:28:18 +08:00
401802709e pcb: Relocate programming hdrs to an accessible place
- Even after the MCU EXT mezzanine is installed
2023-11-30 11:11:17 +08:00
66b6cd28d5 sch: Add install Instructions for Power Resistor 2023-11-30 11:10:20 +08:00
c053eca22a Add Manufacturer into PM1202's Value & Comment 2023-11-29 16:37:35 +08:00
76480a3679 Add Front Panel MFR_PN 2023-11-29 16:32:18 +08:00
08133e5e95 sch, pcb: Add TAN Caps to all LT304x SET Pin
- Prevent noise due to microphonics to be amplified by internal Amp
- Remove the input TAN Caps as LT304x PSRR is very good
- Replace TAN Caps in the 12V input side to be ELEC Cap
    - Save cost
2023-11-29 15:06:26 +08:00
74524b70e4 Scripts: Grab correct KICAD7_3DMODEL_DIR now
- Todo: Use default.nix or flake.nix to setup the path
2023-11-29 15:05:47 +08:00
13720b3ccc Reassign Reference Designators for all Symbols 2023-11-29 10:47:38 +08:00
f558f62313 sch: Add Mounting Screw Symbol and MFR/PN 2023-11-29 10:47:16 +08:00
a8ac943190 Cleanup and Update Modification Date 2023-11-28 11:44:52 +08:00
2612acc9f7 Scripts: Comment Filed is included in the BOM 2023-11-28 10:42:26 +08:00
06a00befeb 3D: Update 3D models of KIrdy LD Adapter 2023-11-28 10:42:26 +08:00
1b7940871b sch, pcb: Add 12V & Mounting holes to MCU EXT HDR 2023-11-28 10:42:20 +08:00
83506fd3c6 sch, pcb: add tantalum C0G Caps for 8V out LT3045 2023-11-27 17:37:52 +08:00
f24f037348 sch, pcb: Change kirdy LD adpter connectors
- Add two extra mounting holes for kirdy LD adapter
- Update kirdy LD adapter 3D model
- Update the PCB layout accordingly
2023-11-27 17:37:52 +08:00
95494ee031 sch, pcb: Add LPF and Buffer for TEC VREF 2023-11-27 17:37:52 +08:00
e7a7eee202 sch, pcb: Remove X7R, X5R at input LT304x
- Reduce the number of Tantalum Capacitor Used
- Replace some non critical ones with Electrolytic Caps
2023-11-27 17:37:52 +08:00
f29c460e72 Add: Footprints and Step Model for Caps
- SMD ELEC: 865080345012
- SMD C0G Ceramic GRMJN65C1H104JE01J
2023-11-27 17:37:52 +08:00
5f7743698e pcb: Add reference designators for connectors, SWs
- SMA Connector, USB Type C, Power Jack, RJ45
- MCU Programming Headers and Boot 0 Headers
- Termination Resistor SW, Modulation Depth SW
2023-11-27 17:37:52 +08:00
43903708c3 sch, pcb: Replace FB of -6V +15V LDO with inductor
- Build a Pi LPF on the input side
2023-11-27 17:37:52 +08:00
24637b4216 sch, pcb: Add alternate footprint for LTC6655 Vref 2023-11-27 17:37:52 +08:00
2cbab29c4e sch, pcb: Add LEDs and TPs to Critical Power Rails 2023-11-27 17:37:52 +08:00
c59eccaa7d sch, pcb: add 0R for TEC Vref Ouput
- For debugging if needed
2023-11-27 17:37:52 +08:00
db54e6cfa8 sch, pcb:Edit PCB shape for connectors to protrude
- Connectors now protrude the front panel
- Align the connectors by the outline generated from 3D Model
- Update the front panel symbol to include the two mounting holes
2023-11-27 17:37:52 +08:00
e0989a61f2 Add Front Panel FreeCAD Assembly
- Static Handle
- PCB Brackets
- Kirdy Front Panel Cutout
2023-11-27 17:37:47 +08:00
13a90dd642 3D_Model: Update 204-121ST 2023-11-21 11:46:48 +08:00
b901f84d0a sch, pcb: Add PWR, POE_PWR netclasses 2023-11-21 11:46:46 +08:00
20198f5eab drc: Check PWR nets clearance on pri and sec sides
- Pri: PoE PWR nets
- Sec: PWR nets like GND, 3V3 etc
2023-11-21 11:46:39 +08:00
47a30da9b1 Port front panel markings design to Kicad
- Front panel text markings can now be modified with Kicad
2023-11-17 15:57:55 +08:00
de7c27c21f sch, pcb: Add mounting holes for Kirdy LD Adapter 2023-11-17 15:42:43 +08:00
41db8612c0 pcb: relocate switches for better accessibility
- modulation depth SW and termination SW are relocated
2023-11-15 17:12:05 +08:00
de3e034c7a Add Front Panel, Kirdy LD Adapter 3D models
- Update sch, pcb, sym lib, footrprint lib
- Position of Kirdy LD Adapter is relocated so that it is symmetric
2023-11-15 17:11:51 +08:00
9f3793c8fb pcb: Add 3D Models 2023-11-10 17:32:29 +08:00
0b99a8f119 sch, pcb: Correct MFR/PN and optimize BOM 2023-11-10 15:18:22 +08:00
7c72afe55f Remove old production files 2023-11-10 15:18:21 +08:00
cd679cf0da sch: Update Title Block Info
- rev0.3 -> rev0_3
- Correct the title of each schematics
- Update the modified time
2023-11-10 15:18:21 +08:00
35da9f8c58 scripts: Add scripts to generate production files
- The following files can be generated from the script.
1. Zipped(Gerber, Drill, Drill Map)
2. Bom,
3. Component Placement
4. Schematics PDF
5. Step Files
2023-11-10 15:18:17 +08:00
5ad5914748 sch, pcb: exclude MHs and soldering JP from BOM 2023-11-09 15:24:07 +08:00
a30ac45c5f pcb: Remove "designed by" silkscreen 2023-11-08 11:53:18 +08:00
13b5f661c5 pcb: Fix TEC Polarity Connections to Header
- Fix Issue #27
2023-11-08 11:53:07 +08:00
7aa84d4d23 sch: Fix incorrect TEC polarity in thermostat
- Fix Issue #27
2023-11-08 11:52:51 +08:00
7b5df5150f thermostat: Fix wrong P/N in TEC Current Sense Res
- Fix Issue #26
2023-11-08 11:13:38 +08:00
2a6ad78f51 pcb: Finish Layout for rev0_3
- Assign MFR_PN for all Components
- schematics changes:
  - drivestage: Add Switch to optionally enable Modulation Signal Termination
  -             Add alternate Precision Power Resistor
  -             Modify the RC network values at TIA LPF Output
  - MCU: Add Redundant 2.54mm pitch Programming Header
  - thermostat: Duplicate the power filter network for alternate Temperature ADC
2023-11-02 15:24:26 +08:00
352f8c075d footprint: Add TL082Hx TI SOIC-8 footprint 2023-10-31 11:02:47 +08:00
0c3c8a3fd1 sch: Update power related flags and nets symbols
- Update the symbol from the kicad 7 built-in library
- Remove ERC warnings
2023-10-31 10:29:43 +08:00
fc02f24131 sch: correct POE_VC* pins name case
- PoE_VC* -> POE_VC*
2023-10-31 10:23:07 +08:00
caf69e4a0f symbol: correct RJ45 VC output pin type
- from power input to power output
2023-10-31 10:21:18 +08:00
b0525c4d74 symbol: AD7172-4 sets DNC pin to unconnected type 2023-10-30 17:40:40 +08:00
1f9b4e9900 sch: fix Temperature ADC SPI Connections
- Fix Issue #25
2023-10-30 17:32:43 +08:00
395e104575 sch: add lpf at TEC_VSEN Buffer Output 2023-10-30 17:29:44 +08:00
86f5addbad sch: Correct typos in TEC_~{SHDN} ports 2023-10-30 12:17:26 +08:00
f66625e431 sch: Add redundant 2.54mm SWD Header 2023-10-27 17:45:39 +08:00
fcae5b785e sch: Correct SWD Header MF/PN and Update Footprint
- Use Adafuit 4048 Mini SWD Headers
- Silkscreen is modified to indicate orientation of the header
2023-10-27 17:42:46 +08:00
89dab2b553 sch: Change PoE RJ45 Jack and change PM1202 Symbol
- Use the same PoE RJ45 as sinara-hw thermostat
- Add PM1202 Power input pins (VB+, VB-)
- Remove PoE softstart circuit as PM1202 has inrush current limiting
- Add Pi Filter at the output of PM1202
2023-10-27 15:33:39 +08:00
929ff58706 sch: Set DNP for DNP components 2023-10-25 17:36:20 +08:00
57e013c9c5 sch: Support Temp ADC in alternate footprint
- Issue #12
- Add Alternate AD7172-4BCPZ circuitry, symbol, footprint and 3D model
2023-10-25 17:36:20 +08:00
d2c80458aa sch: Do not pass MCU RST to ETH
- D3 -> DNP
2023-10-25 17:36:20 +08:00
f732b9944a sch: Fix Issue #14 2023-10-25 17:36:20 +08:00
f1bda76636 sch: correct ethernet phy sigs connections to ESD
- Pull up eth signals with 100R instead of pull down
2023-10-25 17:36:20 +08:00
3a1dce0107 sch: Tune LD- Out Series RC Network
- R98 3R3 -> 10R
- C192 100n PPS -> DNP
- Add C199 2n2 in parallel C192
2023-10-25 17:36:20 +08:00
1fad3bf64d sch: Tune the LD V-I Output Stage Feedback Network
- R67 -> 0R
- C175 -> 100pF
2023-10-25 17:36:20 +08:00
e62bf3b8d6 footprint: Correct PM1202 footprint
- enlarge courtyard and silkscreen to reflect the clearance requirement so that it can be fully seated onto the PCB
2023-10-25 17:36:20 +08:00
dfeb1ec6a8 sch: LD DAC add parallel Cap to output resistor
- Increase the Mod_In Signal Bandwidth
- See Issue #22
2023-10-25 17:36:20 +08:00
2df59fbce9 sch: Use TL082 for PD_Mon TIA and LPF Stage 2023-10-25 17:36:20 +08:00
893f5220c6 sch: Add REF3033 for MCU ADC VREF 2023-10-25 17:36:20 +08:00
01d0e1d45b sch: Modify dsupply freq_comp network
- See Issue #21
2023-10-25 17:36:20 +08:00
566bf0317a sch: Fix Issue #15 2023-10-25 17:36:14 +08:00
3ba3ef159e sch: Add soft start to 12V PWR Jack input 2023-10-25 17:36:14 +08:00
5ffc2a1865 pcb: migrate to kicad 7 2023-10-25 17:35:58 +08:00
8e5545f9c4 sch: R13 Power Resistor change to PDY10R000F 2023-10-12 12:43:03 +08:00
fcdabaee9c Mirgrate to kicad7 2023-10-12 12:26:04 +08:00
106 changed files with 858566 additions and 1014651 deletions

8
.gitignore vendored
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@ -3,6 +3,9 @@
# Temporary files
*.000
*.cache
*.config
*.local
*.bak
*.bck
*.kicad_pcb-bak
@ -17,6 +20,8 @@ _autosave-*
*-save.kicad_pcb
fp-info-cache
*auto_saved_files*
~*
__pycache__
# Netlist files (exported from Eeschema)
*.net
@ -24,3 +29,6 @@ fp-info-cache
# Autorouter files (exported from Pcbnew)
*.dsn
*.ses
# Generated Production Files
result

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19
Panel/README.md Normal file
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@ -0,0 +1,19 @@
# Kirdy Front Panel
## Front Panel Text Markings
- Font: PrisonGothicPro-Medium.otf
- Drawn in KiCAD 7
## Front Panel Mechanical Design and Drawings
- Drawn in FreeCAD 0.21.2 with a2plus and Exploded Assembly Workbench installed
- Reference Assembly Kit: nVent SCHROFF 20848-668
- Reference drawings: https://git.m-labs.hk/sinara-hw/front-panels/src/branch/master/Kasli_SOC-vNone
## Front Panel Fiber Optic Adapter Mounting Plates
- Drawn in KiCAD 7
- Mounting Plate can be manufactured as 1.5 mm Aluminum Plate or 1.6 mm Single Layer Aluminum PCB
- Possible Fiber Optic Adapter Compatible for Each Type of Mounting Plate
- Type 1: SC to SC Fibre Optic Adapter
![](images/SC_To_SC_Fiber_Optic_Adapter.jpg)
- Type 2: FC to FC Fiber Optic Adapter
![](images/FC_To_FC_Fiber_Optic_Adapter.jpg)

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{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"board_outline_line_width": 0.049999999999999996,
"copper_line_width": 0.19999999999999998,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": false,
"courtyard_line_width": 0.049999999999999996,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 0,
"units_format": 1
},
"fab_line_width": 0.09999999999999999,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.09999999999999999,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 0.762,
"height": 1.524,
"width": 1.524
},
"silk_line_width": 0.09999999999999999,
"silk_text_italic": false,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.09999999999999999,
"silk_text_upright": false,
"zones": {
"min_clearance": 0.5
}
},
"diff_pair_dimensions": [],
"drc_exclusions": [],
"meta": {
"version": 2
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint": "error",
"footprint_type_mismatch": "ignore",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"lib_footprint_issues": "warning",
"lib_footprint_mismatch": "warning",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "warning",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_edge_clearance": "warning",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"solder_mask_bridge": "error",
"starved_thermal": "error",
"text_height": "warning",
"text_thickness": "warning",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zones_intersect": "error"
},
"rules": {
"max_error": 0.005,
"min_clearance": 0.0,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.5,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_resolved_spokes": 2,
"min_silk_clearance": 0.0,
"min_text_height": 0.7999999999999999,
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.0,
"min_via_annular_width": 0.09999999999999999,
"min_via_diameter": 0.5,
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
"teardrop_options": [
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 5,
"td_on_pad_in_zone": false,
"td_onpadsmd": true,
"td_onroundshapesonly": false,
"td_ontrackend": false,
"td_onviapad": true
}
],
"teardrop_parameters": [
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_round_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_rect_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_track_end",
"td_width_to_size_filter_ratio": 0.9
}
],
"track_widths": [],
"via_dimensions": [],
"zones_allow_external_fillets": false
},
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "kirdy_fp_fiber_optic_ adapter_mounting_plate_type_1.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.2,
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6
}
],
"meta": {
"version": 3
},
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": []
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"specctra_dsn": "",
"step": "../output/FP_1550_Fiber_Optic_Adapter_Mounting_Plate_Type_1/FP_1550_Fiber_Optic_Adapter_Mounting_Plate_Type_1_r0_1rc1.step",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"legacy_lib_dir": "",
"legacy_lib_list": []
},
"sheets": [],
"text_variables": {}
}

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@ -0,0 +1,229 @@
{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"board_outline_line_width": 0.049999999999999996,
"copper_line_width": 0.19999999999999998,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": false,
"courtyard_line_width": 0.049999999999999996,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 0,
"units_format": 1
},
"fab_line_width": 0.09999999999999999,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.09999999999999999,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 0.762,
"height": 1.524,
"width": 1.524
},
"silk_line_width": 0.09999999999999999,
"silk_text_italic": false,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.09999999999999999,
"silk_text_upright": false,
"zones": {
"min_clearance": 0.5
}
},
"diff_pair_dimensions": [],
"drc_exclusions": [],
"meta": {
"version": 2
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint": "error",
"footprint_type_mismatch": "ignore",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"lib_footprint_issues": "warning",
"lib_footprint_mismatch": "warning",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "warning",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_edge_clearance": "warning",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"solder_mask_bridge": "error",
"starved_thermal": "error",
"text_height": "warning",
"text_thickness": "warning",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zones_intersect": "error"
},
"rules": {
"max_error": 0.005,
"min_clearance": 0.0,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.5,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_resolved_spokes": 2,
"min_silk_clearance": 0.0,
"min_text_height": 0.7999999999999999,
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.0,
"min_via_annular_width": 0.09999999999999999,
"min_via_diameter": 0.5,
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
"teardrop_options": [
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 5,
"td_on_pad_in_zone": false,
"td_onpadsmd": true,
"td_onroundshapesonly": false,
"td_ontrackend": false,
"td_onviapad": true
}
],
"teardrop_parameters": [
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_round_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_rect_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_track_end",
"td_width_to_size_filter_ratio": 0.9
}
],
"track_widths": [],
"via_dimensions": [],
"zones_allow_external_fillets": false
},
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "kirdy_fp_fiber_optic_adapter_mounting_plate_type_2.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.2,
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6
}
],
"meta": {
"version": 3
},
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": []
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"specctra_dsn": "",
"step": "../output/FP_1550_Fiber_Optic_Adapter_Mounting_Plate_Type_2/FP_1550_Fiber_Optic_Adapter_Mounting_Plate_Type_2_r0_1rc1.step",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"legacy_lib_dir": "",
"legacy_lib_list": []
},
"sheets": [],
"text_variables": {}
}

View File

@ -0,0 +1,86 @@
{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"board_outline_line_width": 0.1,
"copper_line_width": 0.2,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"other_line_width": 0.15,
"silk_line_width": 0.15,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.15
},
"diff_pair_dimensions": [],
"drc_exclusions": [],
"rules": {
"min_copper_edge_clearance": 0.0,
"solder_mask_clearance": 0.0,
"solder_mask_min_width": 0.0
},
"track_widths": [],
"via_dimensions": []
},
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "kirdy_fp_fiber_optic_adapter_mounting_plates.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6
}
],
"meta": {
"version": 3
},
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": []
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"specctra_dsn": "",
"step": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"legacy_lib_dir": "",
"legacy_lib_list": []
},
"sheets": [],
"text_variables": {}
}

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{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"board_outline_line_width": 0.049999999999999996,
"copper_line_width": 0.19999999999999998,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": false,
"courtyard_line_width": 0.049999999999999996,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": false,
"text_position": 0,
"units_format": 1
},
"fab_line_width": 0.09999999999999999,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.09999999999999999,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 0.762,
"height": 1.524,
"width": 1.524
},
"silk_line_width": 0.09999999999999999,
"silk_text_italic": false,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.09999999999999999,
"silk_text_upright": false,
"zones": {
"min_clearance": 0.5
}
},
"diff_pair_dimensions": [],
"drc_exclusions": [],
"meta": {
"version": 2
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint": "error",
"footprint_type_mismatch": "ignore",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"lib_footprint_issues": "warning",
"lib_footprint_mismatch": "warning",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "warning",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_edge_clearance": "warning",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"solder_mask_bridge": "error",
"starved_thermal": "error",
"text_height": "warning",
"text_thickness": "warning",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zones_intersect": "error"
},
"rules": {
"max_error": 0.005,
"min_clearance": 0.0,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.5,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_resolved_spokes": 2,
"min_silk_clearance": 0.0,
"min_text_height": 0.7999999999999999,
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.0,
"min_via_annular_width": 0.09999999999999999,
"min_via_diameter": 0.5,
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
"teardrop_options": [
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 5,
"td_on_pad_in_zone": false,
"td_onpadsmd": true,
"td_onroundshapesonly": false,
"td_ontrackend": false,
"td_onviapad": true
}
],
"teardrop_parameters": [
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_round_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_rect_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_track_end",
"td_width_to_size_filter_ratio": 0.9
}
],
"track_widths": [],
"via_dimensions": [],
"zones_allow_external_fillets": false
},
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "kirdy_front_panel_markings.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.2,
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6
}
],
"meta": {
"version": 3
},
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": []
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"specctra_dsn": "",
"step": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"legacy_lib_dir": "",
"legacy_lib_list": []
},
"sheets": [],
"text_variables": {}
}

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44
flake.lock generated Normal file
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@ -0,0 +1,44 @@
{
"nodes": {
"kicad_bom_generator": {
"flake": false,
"locked": {
"lastModified": 1702353729,
"narHash": "sha256-NIM/GLC71VdGdMletBBv9lSPuHpgD9zzeGiVQLEAULA=",
"ref": "refs/heads/main",
"rev": "72686f5556785c9aa13678dc42757dddfb7d7c23",
"revCount": 2,
"type": "git",
"url": "https://git.m-labs.hk/M-Labs/KiCAD_BOM_Generator.git"
},
"original": {
"type": "git",
"url": "https://git.m-labs.hk/M-Labs/KiCAD_BOM_Generator.git"
}
},
"nixpkgs": {
"locked": {
"lastModified": 1703467016,
"narHash": "sha256-/5A/dNPhbQx/Oa2d+Get174eNI3LERQ7u6WTWOlR1eQ=",
"owner": "NixOS",
"repo": "nixpkgs",
"rev": "d02d818f22c777aa4e854efc3242ec451e5d462a",
"type": "github"
},
"original": {
"owner": "NixOS",
"ref": "nixos-23.11",
"repo": "nixpkgs",
"type": "github"
}
},
"root": {
"inputs": {
"kicad_bom_generator": "kicad_bom_generator",
"nixpkgs": "nixpkgs"
}
}
},
"root": "root",
"version": 7
}

67
flake.nix Normal file
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{
inputs.nixpkgs.url = "github:NixOS/nixpkgs/nixos-23.11";
inputs.kicad_bom_generator = {
url = "git+https://git.m-labs.hk/M-Labs/KiCAD_BOM_Generator.git";
flake = false;
};
outputs = { self, nixpkgs, kicad_bom_generator }: {
formatter.x86_64-linux = nixpkgs.legacyPackages.x86_64-linux.nixfmt;
devShells.x86_64-linux.default =
let pkgs = nixpkgs.legacyPackages.x86_64-linux;
in pkgs.mkShell {
name = "kicad-dev-shell";
buildInputs = [ pkgs.kicad ];
};
defaultPackage.x86_64-linux =
with import nixpkgs { system = "x86_64-linux"; };
stdenv.mkDerivation {
name = "production_files";
src = ./src;
nativeBuildInputs = [ pkgs.kicad pkgs.zip pkgs.python3 ];
buildPhase = ''
# kicad-cli requires the use of $HOME
TMP_DIR="$(mktemp --tmpdir -d kicad-kirdy.XXXXXXX)"
export HOME=$TMP_DIR
SCH=kirdy.kicad_sch
PCB=kirdy.kicad_pcb
# Get Revision Number from the Title Block in KiCAD Top Schematics
REV=$(cat $SCH | grep rev | cut -d'"' -f 2)
PREFIX=kirdy_$REV
kicad-cli sch export python-bom $SCH -o $PREFIX"_bom".xml
export PYTHONPATH=${pkgs.kicad.base}/share/kicad/plugins
python ${kicad_bom_generator}/generate_bom_from_xml.py $PREFIX"_bom".xml $PREFIX"_bom".csv
kicad-cli sch export pdf $SCH -o $PREFIX.pdf
kicad-cli pcb export pos $PCB --format csv --units mm -o $PREFIX"_pos".csv
export KICAD7_3DMODEL_DIR=${pkgs.kicad.libraries.packages3d}/share/kicad/3dmodels
kicad-cli pcb export step $PCB --subst-models --force -o $PREFIX.step
mkdir -p $PREFIX"_gerber_drill"
kicad-cli pcb export gerbers $PCB -l 'F.Cu,In1.Cu,In2.Cu,B.Cu,F.Paste,B.Paste,F.Silkscreen,B.Silkscreen,F.Mask,B.Mask,Edge.Cuts' --no-x2 --subtract-soldermask -o ./$PREFIX"_gerber_drill"
# The additional trailing slash is due to a bug in the kicad-cli tool. https://gitlab.com/kicad/code/kicad/-/issues/14438
kicad-cli pcb export drill $PCB -u mm --generate-map --map-format gerberx2 -o ./$PREFIX"_gerber_drill"/
zip -r -j $PREFIX"_gerber_drill" $PREFIX"_gerber_drill"
'';
installPhase = ''
mkdir -p $out/production_files
cp $PREFIX"_bom".csv $out/production_files/$PREFIX"_bom".csv
cp $PREFIX.pdf $out/production_files/$PREFIX.pdf
cp $PREFIX"_pos".csv $out/production_files/$PREFIX"_pos.csv"
cp $PREFIX.step $out/production_files/$PREFIX.step
cp $PREFIX"_gerber_drill".zip $out/production_files/$PREFIX"_gerber_drill".zip
'';
};
};
}

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@ -1,51 +0,0 @@
(footprint "LCC127P500X500X155-8N" (version 20211014) (generator pcbnew)
(layer "F.Cu")
(tedit 62A71DC4)
(attr through_hole)
(fp_text reference "REF**" (at 0.887085 -5.973065) (layer "F.SilkS")
(effects (font (size 1.909205 1.909205) (thickness 0.15)))
(tstamp 3cb443b0-116f-45d7-9f4a-e4e7948e4bac)
)
(fp_text value "LCC127P500X500X155-8N" (at 18.839705 5.143665) (layer "F.Fab")
(effects (font (size 1.897709 1.897709) (thickness 0.15)))
(tstamp f0edf902-9b2c-4ebc-8439-ef9fcc9a7242)
)
(fp_line (start -1.2954 -2.5654) (end -2.5654 -2.5654) (layer "F.SilkS") (width 0.1524) (tstamp 2e65d6a3-f462-4596-86f1-13bfcc504d77))
(fp_line (start -2.5654 1.9304) (end -2.5654 2.5654) (layer "F.SilkS") (width 0.1524) (tstamp 3b4faed2-9b3e-4cd7-8f24-0291f6757e0c))
(fp_line (start 2.5654 2.5654) (end 2.5654 1.9304) (layer "F.SilkS") (width 0.1524) (tstamp 5252f3ef-7140-4924-88b6-36f3a36595ad))
(fp_line (start -1.9558 -1.9304) (end -1.2954 -2.5654) (layer "F.SilkS") (width 0.1524) (tstamp 8bd93de9-cf43-4ab6-b3c4-eda19e34b099))
(fp_line (start -0.6604 -2.5654) (end -1.2954 -2.5654) (layer "F.SilkS") (width 0.1524) (tstamp b5ea1b82-2b65-499f-bed5-9bfbe191900e))
(fp_line (start -2.5654 -2.5654) (end -2.5654 -1.9304) (layer "F.SilkS") (width 0.1524) (tstamp b6569a7c-252a-4a87-815e-69d3a00611eb))
(fp_line (start 2.5654 -1.9304) (end 2.5654 -2.5654) (layer "F.SilkS") (width 0.1524) (tstamp c8ba6ab1-227f-4eae-93f0-ac248e1c6a60))
(fp_line (start 2.5654 -2.5654) (end 0.6604 -2.5654) (layer "F.SilkS") (width 0.1524) (tstamp c94437c5-f1bb-4b9e-85b3-adca27c5f189))
(fp_line (start -2.5654 2.5654) (end -0.6604 2.5654) (layer "F.SilkS") (width 0.1524) (tstamp db62d487-db93-4579-8349-05f96946c119))
(fp_line (start 0.6604 2.5654) (end 2.5654 2.5654) (layer "F.SilkS") (width 0.1524) (tstamp f2c0dea5-1b82-4194-b151-aa763c17445b))
(fp_line (start 3.1242 -3.1242) (end 3.1242 3.1242) (layer "F.CrtYd") (width 0.1524) (tstamp 03488fbd-f9b2-4b83-bf6a-547321f3f27f))
(fp_line (start 3.1242 3.1242) (end -3.1242 3.1242) (layer "F.CrtYd") (width 0.1524) (tstamp 98233968-f58c-4ba3-ab92-bed6e69c9bff))
(fp_line (start -3.1242 3.1242) (end -3.1242 -3.1242) (layer "F.CrtYd") (width 0.1524) (tstamp 9f15e76b-9d3c-43f8-8c88-45b5f0f40657))
(fp_line (start -3.1242 -3.1242) (end 3.1242 -3.1242) (layer "F.CrtYd") (width 0.1524) (tstamp d567a8ae-d9e6-4487-a8da-4ce4624cf321))
(fp_line (start -2.5654 -2.5654) (end -2.5654 2.5654) (layer "F.Fab") (width 0.1524) (tstamp 0acac716-cc7f-48fc-84fa-cd71ddb74d73))
(fp_line (start 0.3048 -2.5654) (end -0.3048 -2.5654) (layer "F.Fab") (width 0.1524) (tstamp 18508540-fca5-4baa-bf54-69bf19bb602b))
(fp_line (start -0.3048 2.5654) (end 0.3048 2.5654) (layer "F.Fab") (width 0.1524) (tstamp 3f32606b-98ed-4c01-8464-57e08c6034c6))
(fp_line (start -2.5654 0.9652) (end -2.5654 1.5748) (layer "F.Fab") (width 0.1524) (tstamp 4581d794-f4d8-446c-8128-878966f1f92f))
(fp_line (start 2.5654 0.3048) (end 2.5654 -0.3048) (layer "F.Fab") (width 0.1524) (tstamp 542df30c-2cfd-493a-9dd1-37cabc66d363))
(fp_line (start 2.5654 2.5654) (end 2.5654 -2.5654) (layer "F.Fab") (width 0.1524) (tstamp 5e70b20d-4386-4f30-9f32-b8a80e56ab67))
(fp_line (start -2.5654 -1.2954) (end -1.2954 -2.5654) (layer "F.Fab") (width 0.1524) (tstamp 6bdd7ed3-2432-47ef-8a66-1d46819e58dc))
(fp_line (start -2.5654 -0.3048) (end -2.5654 0.3048) (layer "F.Fab") (width 0.1524) (tstamp a770f08e-8ab5-4ff0-a5b5-5211ad23fcc9))
(fp_line (start -2.5654 2.5654) (end 2.5654 2.5654) (layer "F.Fab") (width 0.1524) (tstamp af247e64-4e93-40be-ba8e-f25a266edc8e))
(fp_line (start 2.5654 -2.5654) (end -2.5654 -2.5654) (layer "F.Fab") (width 0.1524) (tstamp bd31ec8d-7951-4b54-8637-22492b127da8))
(fp_line (start 2.5654 1.5748) (end 2.5654 0.9652) (layer "F.Fab") (width 0.1524) (tstamp fcbab7ff-ba48-413e-8097-7a176acb0199))
(pad "1" smd rect (at -2.2352 -1.27 270) (size 0.635 1.2954) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp f230bf0e-7a7a-4c7c-a46f-eb1797d1e176))
(pad "2" smd rect (at -2.2352 0 270) (size 0.635 1.2954) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp dbbe0bd5-3107-43a4-b3d9-fe56460133d1))
(pad "3" smd rect (at -2.2352 1.27 270) (size 0.635 1.2954) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp e910cdcd-1a44-4910-b369-6dc0c0af99bd))
(pad "4" smd rect (at 0 2.2352 180) (size 0.635 1.2954) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 0e8aad71-f643-4f1a-be58-deca9d183299))
(pad "5" smd rect (at 2.2352 1.27 270) (size 0.635 1.2954) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 7c758830-e591-4e69-a8e1-e8f2523f8fbf))
(pad "6" smd rect (at 2.2352 0 270) (size 0.635 1.2954) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 29296804-373f-45cb-868b-e617622cfc89))
(pad "7" smd rect (at 2.2352 -1.27 270) (size 0.635 1.2954) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp aa8da901-d1e5-4f8f-b624-900a20b18792))
(pad "8" smd rect (at 0 -1.7272 180) (size 0.635 2.3114) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 36667124-0756-40e9-bb1f-75d5487923c2))
(model "${KIPRJMOD}/kirdy.pretty/FKH0008A.stp"
(offset (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)

View File

@ -1,45 +0,0 @@
(footprint "PM1202" (version 20211014) (generator pcbnew)
(layer "F.Cu")
(tedit 6314C2F6)
(attr through_hole)
(fp_text reference "REF**" (at 27.94 0 unlocked) (layer "F.SilkS")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 5c90fee6-64a7-4748-b73d-fb880ce13cf1)
)
(fp_text value "PM1202" (at 1.4 -3.7 unlocked) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 4348725f-78f2-44b9-884d-46648379c99e)
)
(fp_text user "${REFERENCE}" (at 9.4 -3.8 unlocked) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp aeafd2d5-7ab5-4c2c-88e9-934994ab193e)
)
(fp_line (start 48.666 2.3) (end 60.859 2.3) (layer "F.SilkS") (width 0.05) (tstamp 306ec2cb-449c-436d-8b27-6c6c6a0903a5))
(fp_line (start 31.67 10.7) (end 48.666 10.7) (layer "F.SilkS") (width 0.05) (tstamp 3f8d04eb-14b7-45cc-b91d-39643f918dbc))
(fp_line (start -1.27 2.3) (end 31.67 2.3) (layer "F.SilkS") (width 0.05) (tstamp 93d17a0d-46db-4823-8a92-4ba37acf4cbd))
(fp_line (start 31.67 2.3) (end 31.67 10.7) (layer "F.SilkS") (width 0.05) (tstamp a4a64db0-3332-4613-9acd-a2615645f1f2))
(fp_line (start 48.666 10.7) (end 48.666 2.3) (layer "F.SilkS") (width 0.05) (tstamp b03d0023-6e95-4af0-9b2d-0638acfa4d71))
(fp_line (start -1.27 -7.3) (end -1.27 2.3) (layer "F.SilkS") (width 0.05) (tstamp ca5515e5-3523-4407-9647-1b5bf038e4f1))
(fp_line (start 60.859 0) (end 60.859 2.3) (layer "F.SilkS") (width 0.05) (tstamp d9f661a8-5931-4a8d-a364-3712d92e39b5))
(fp_line (start -1.27 -7.3) (end 60.859 -7.3) (layer "F.SilkS") (width 0.05) (tstamp db35ad12-f3c2-4b03-b3af-be4724bcb3a4))
(fp_line (start 60.859 0) (end 60.859 -7.3) (layer "F.SilkS") (width 0.05) (tstamp eb8751bc-dcef-475b-b0ce-bb2bb82080ee))
(fp_line (start 31.67 2.3) (end 31.67 10.7) (layer "F.CrtYd") (width 0.05) (tstamp 25b0aa80-baee-43a0-b506-7c917421cfce))
(fp_line (start 48.666 10.7) (end 48.666 2.3) (layer "F.CrtYd") (width 0.05) (tstamp 4c0077bb-94a6-4281-a330-706c8cb25429))
(fp_line (start 31.67 10.7) (end 48.666 10.7) (layer "F.CrtYd") (width 0.05) (tstamp 99fae3ed-3f7d-4a12-86da-00d83880beac))
(fp_line (start -1.27 -7.3) (end 60.859 -7.3) (layer "F.CrtYd") (width 0.05) (tstamp 9f5d5a4d-3d22-44ef-bbfb-5bc191ab05c5))
(fp_line (start -1.27 -7.3) (end -1.27 2.3) (layer "F.CrtYd") (width 0.05) (tstamp a878e5f4-5345-4e34-b881-422fbcd57f48))
(fp_line (start 48.666 2.3) (end 60.859 2.3) (layer "F.CrtYd") (width 0.05) (tstamp bc20a622-40bb-4af3-9d07-442432c8c91e))
(fp_line (start 60.859 0) (end 60.859 -7.3) (layer "F.CrtYd") (width 0.05) (tstamp c16d2b9a-1c39-4800-8c04-47ccda6c6d03))
(fp_line (start -1.27 2.3) (end 31.67 2.3) (layer "F.CrtYd") (width 0.05) (tstamp dac09663-b061-490c-ba0c-75a4a61b1612))
(fp_line (start 60.859 0) (end 60.859 2.3) (layer "F.CrtYd") (width 0.05) (tstamp fb70420b-90c7-4b5b-8323-ed4b18da56ab))
(pad "1" thru_hole roundrect (at 0 0) (size 1.8 3) (drill 1.1) (layers *.Cu *.Mask) (roundrect_rratio 0.25) (tstamp c77258b1-5265-4446-bd4f-bb39fc9fe986))
(pad "2" thru_hole roundrect (at 2.54 0) (size 1.8 3) (drill 1.1) (layers *.Cu *.Mask) (roundrect_rratio 0.25) (tstamp ae3c1221-a098-49a1-8631-f067c74b1e08))
(pad "3" thru_hole roundrect (at 5.08 0) (size 1.8 3) (drill 1.1) (layers *.Cu *.Mask) (roundrect_rratio 0.25) (tstamp 13ca2e3f-659f-42d6-b273-7529532992c2))
(pad "4" thru_hole roundrect (at 7.62 0) (size 1.8 3) (drill 1.1) (layers *.Cu *.Mask) (roundrect_rratio 0.25) (tstamp 0dac0b26-cc05-4f21-89e2-2ea38003e73f))
(pad "5" thru_hole roundrect (at 10.16 0) (size 1.8 3) (drill 1.1) (layers *.Cu *.Mask) (roundrect_rratio 0.25) (tstamp 1b7e0f42-4467-4e80-8012-337024ae5fba))
(pad "6" thru_hole roundrect (at 12.7 0) (size 1.8 3) (drill 1.1) (layers *.Cu *.Mask) (roundrect_rratio 0.25) (tstamp 8e142d6a-c56f-4d47-ae5c-d64e5593baf6))
(pad "7" thru_hole roundrect (at 52.202 0) (size 1.8 3) (drill 1.1) (layers *.Cu *.Mask) (roundrect_rratio 0.25) (tstamp 9e7e18e1-302a-4340-812a-4b4f0207c545))
(pad "8" thru_hole roundrect (at 54.742 0) (size 1.8 3) (drill 1.1) (layers *.Cu *.Mask) (roundrect_rratio 0.25) (tstamp f1ee8936-b66c-499a-bb0c-011645be4b90))
(pad "9" thru_hole roundrect (at 57.282 0) (size 1.8 3) (drill 1.1) (layers *.Cu *.Mask) (roundrect_rratio 0.25) (tstamp 21bc1437-5943-4214-b89d-8d1f5af94ac7))
(pad "10" thru_hole roundrect (at 59.822 0) (size 1.8 3) (drill 1.1) (layers *.Cu *.Mask) (roundrect_rratio 0.25) (tstamp 153d6c8f-d83a-4010-9433-ae1675f36797))
)

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kirdy.xls

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src/flake.lock generated Normal file
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@ -0,0 +1,27 @@
{
"nodes": {
"nixpkgs": {
"locked": {
"lastModified": 1701952659,
"narHash": "sha256-TJv2srXt6fYPUjxgLAL0cy4nuf1OZD4KuA1TrCiQqg0=",
"owner": "NixOS",
"repo": "nixpkgs",
"rev": "b4372c4924d9182034066c823df76d6eaf1f4ec4",
"type": "github"
},
"original": {
"owner": "NixOS",
"ref": "nixos-23.11",
"repo": "nixpkgs",
"type": "github"
}
},
"root": {
"inputs": {
"nixpkgs": "nixpkgs"
}
}
},
"root": "root",
"version": 7
}

39
src/flake.nix Normal file
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@ -0,0 +1,39 @@
{
inputs.nixpkgs.url = "github:NixOS/nixpkgs/nixos-23.11";
outputs = { self, nixpkgs }: {
devShells.x86_64-linux.default =
let pkgs = nixpkgs.legacyPackages.x86_64-linux;
in pkgs.mkShell {
name = "kicad-dev-shell";
buildInputs = [ pkgs.kicad ];
shellHook = ''
export KICAD7_3DMODEL_DIR=${pkgs.kicad.libraries.packages3d}
export PYTHONPATH=${pkgs.kicad.base}/share/kicad/plugins
export OUTPUT_DIR=$(pwd)/production
'';
};
defaultPackage.x86_64-linux = # Notice the reference to nixpkgs here.
with import nixpkgs { system = "x86_64-linux"; };
stdenv.mkDerivation {
name = "proj";
src = self;
nativeBuildInputs = [ pkgs.kicad pkgs.python3 ];
buildPhase = ''
export HOME=/tmp
echo ${src}
kicad-cli sch export pdf ${src}/kirdy.kicad_sch -o kirdy.pdf
'';
installPhase = "echo test";
};
};
# pkgs = nixpkgs.legacyPackages.x86_64-linux;
# nativeBuildInputs = [
# pkgs.kicad pkgs.python3
# ];
}

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5
src/kirdy.kicad_dru Normal file
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@ -0,0 +1,5 @@
(version 1)
(rule "PoE PWR Clearance Between GND and PoE AC Input"
(constraint clearance (min 1.0mm))
(condition " A.NetClass != B.NetClass && A.NetClass == 'PWR' && B.NetClass == 'POE_PWR' " ))

130563
src/kirdy.kicad_pcb Normal file

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@ -1,5 +1,6 @@
{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"board_outline_line_width": 0.09999999999999999,
@ -72,20 +73,26 @@
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint": "error",
"footprint_type_mismatch": "error",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"lib_footprint_issues": "warning",
"lib_footprint_mismatch": "warning",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
@ -95,9 +102,14 @@
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_edge_clearance": "ignore",
"silk_over_copper": "ignore",
"silk_overlap": "warning",
"silk_overlap": "ignore",
"skew_out_of_range": "error",
"solder_mask_bridge": "error",
"starved_thermal": "error",
"text_height": "warning",
"text_thickness": "warning",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
@ -106,33 +118,78 @@
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zone_has_empty_net": "error",
"zones_intersect": "error"
},
"rules": {
"allow_blind_buried_vias": false,
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.08889999999999999,
"min_copper_edge_clearance": 0.25,
"min_clearance": 0.09,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.3,
"min_hole_clearance": 0.254,
"min_hole_to_hole": 0.254,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_resolved_spokes": 2,
"min_silk_clearance": 0.0,
"min_text_height": 0.7999999999999999,
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.19999999999999998,
"min_track_width": 0.08889999999999999,
"min_track_width": 0.09,
"min_via_annular_width": 0.09999999999999999,
"min_via_diameter": 0.39999999999999997,
"solder_mask_clearance": 0.0,
"solder_mask_min_width": 0.0,
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
"teardrop_options": [
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 5,
"td_on_pad_in_zone": false,
"td_onpadsmd": true,
"td_onroundshapesonly": false,
"td_ontrackend": false,
"td_onviapad": true
}
],
"teardrop_parameters": [
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_round_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_rect_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_track_end",
"td_width_to_size_filter_ratio": 0.9
}
],
"track_widths": [
0.0,
0.0889,
0.146812,
0.254,
0.5,
1.0,
2.0
],
@ -153,7 +210,8 @@
"zones_allow_external_fillets": true,
"zones_use_no_outline": true
},
"layer_presets": []
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
@ -337,18 +395,23 @@
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_label_syntax": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"conflicting_netclasses": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"endpoint_off_grid": "warning",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"missing_bidi_pin": "warning",
"missing_input_pin": "warning",
"missing_power_pin": "error",
"missing_unit": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
@ -358,6 +421,7 @@
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"simulation_model_issue": "ignore",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
@ -375,8 +439,8 @@
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"clearance": 0.0889,
"bus_width": 12,
"clearance": 0.09,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
@ -389,13 +453,70 @@
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6.0
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.09,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "POE_PWR",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.09,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
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3127
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View File

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