303 lines
10 KiB
Rust
303 lines
10 KiB
Rust
#![deny(warnings)]
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#![no_std]
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#![no_main]
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use core::sync::atomic::{fence, Ordering};
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use mutex_trait::prelude::*;
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use dsp::iir;
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use stabilizer::{
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hardware::{
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self,
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adc::{Adc0Input, Adc1Input, AdcCode},
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afe::Gain,
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dac::{Dac0Output, Dac1Output, DacCode},
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embedded_hal::digital::v2::InputPin,
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hal,
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system_timer::SystemTimer,
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DigitalInput0, DigitalInput1, AFE0, AFE1,
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},
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net::{
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data_stream::{BlockGenerator, StreamTarget},
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miniconf::Miniconf,
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serde::Deserialize,
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telemetry::{Telemetry, TelemetryBuffer},
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NetworkState, NetworkUsers,
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},
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};
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const SCALE: f32 = i16::MAX as _;
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// The number of cascaded IIR biquads per channel. Select 1 or 2!
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const IIR_CASCADE_LENGTH: usize = 1;
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#[derive(Clone, Copy, Debug, Deserialize, Miniconf)]
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pub struct Settings {
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afe: [Gain; 2],
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iir_ch: [[iir::IIR; IIR_CASCADE_LENGTH]; 2],
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allow_hold: bool,
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force_hold: bool,
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telemetry_period: u16,
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stream_target: StreamTarget,
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}
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impl Default for Settings {
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fn default() -> Self {
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Self {
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// Analog frontend programmable gain amplifier gains (G1, G2, G5, G10)
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afe: [Gain::G1, Gain::G1],
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// IIR filter tap gains are an array `[b0, b1, b2, a1, a2]` such that the
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// new output is computed as `y0 = a1*y1 + a2*y2 + b0*x0 + b1*x1 + b2*x2`.
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// The array is `iir_state[channel-index][cascade-index][coeff-index]`.
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// The IIR coefficients can be mapped to other transfer function
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// representations, for example as described in https://arxiv.org/abs/1508.06319
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iir_ch: [[iir::IIR::new(1., -SCALE, SCALE); IIR_CASCADE_LENGTH]; 2],
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// Permit the DI1 digital input to suppress filter output updates.
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allow_hold: false,
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// Force suppress filter output updates.
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force_hold: false,
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// The default telemetry period in seconds.
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telemetry_period: 10,
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stream_target: StreamTarget::default(),
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}
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}
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}
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#[rtic::app(device = stabilizer::hardware::hal::stm32, peripherals = true, monotonic = stabilizer::hardware::system_timer::SystemTimer)]
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const APP: () = {
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struct Resources {
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afes: (AFE0, AFE1),
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digital_inputs: (DigitalInput0, DigitalInput1),
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adcs: (Adc0Input, Adc1Input),
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dacs: (Dac0Output, Dac1Output),
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network: NetworkUsers<Settings, Telemetry>,
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generator: BlockGenerator,
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settings: Settings,
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telemetry: TelemetryBuffer,
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#[init([[[0.; 5]; IIR_CASCADE_LENGTH]; 2])]
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iir_state: [[iir::Vec5; IIR_CASCADE_LENGTH]; 2],
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}
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#[init(spawn=[telemetry, settings_update, ethernet_link])]
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fn init(c: init::Context) -> init::LateResources {
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// Configure the microcontroller
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let (mut stabilizer, _pounder) =
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hardware::setup::setup(c.core, c.device);
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let mut network = NetworkUsers::new(
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stabilizer.net.stack,
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stabilizer.net.phy,
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stabilizer.cycle_counter,
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env!("CARGO_BIN_NAME"),
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stabilizer.net.mac_address,
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);
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let generator = network.enable_streaming();
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// Spawn a settings update for default settings.
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c.spawn.settings_update().unwrap();
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c.spawn.telemetry().unwrap();
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// Spawn the ethernet link period check task.
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c.spawn.ethernet_link().unwrap();
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// Enable ADC/DAC events
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stabilizer.adcs.0.start();
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stabilizer.adcs.1.start();
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stabilizer.dacs.0.start();
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stabilizer.dacs.1.start();
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// Start sampling ADCs.
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stabilizer.adc_dac_timer.start();
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init::LateResources {
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afes: stabilizer.afes,
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adcs: stabilizer.adcs,
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dacs: stabilizer.dacs,
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generator,
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network,
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digital_inputs: stabilizer.digital_inputs,
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telemetry: TelemetryBuffer::default(),
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settings: Settings::default(),
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}
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}
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/// Main DSP processing routine for Stabilizer.
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///
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/// # Note
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/// Processing time for the DSP application code is bounded by the following constraints:
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///
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/// DSP application code starts after the ADC has generated a batch of samples and must be
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/// completed by the time the next batch of ADC samples has been acquired (plus the FIFO buffer
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/// time). If this constraint is not met, firmware will panic due to an ADC input overrun.
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///
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/// The DSP application code must also fill out the next DAC output buffer in time such that the
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/// DAC can switch to it when it has completed the current buffer. If this constraint is not met
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/// it's possible that old DAC codes will be generated on the output and the output samples will
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/// be delayed by 1 batch.
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///
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/// Because the ADC and DAC operate at the same rate, these two constraints actually implement
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/// the same time bounds, meeting one also means the other is also met.
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#[task(binds=DMA1_STR4, resources=[adcs, digital_inputs, dacs, iir_state, settings, telemetry, generator], priority=2)]
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#[inline(never)]
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#[link_section = ".itcm.process"]
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fn process(mut c: process::Context) {
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let process::Resources {
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adcs: (ref mut adc0, ref mut adc1),
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dacs: (ref mut dac0, ref mut dac1),
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ref digital_inputs,
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ref settings,
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ref mut iir_state,
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ref mut telemetry,
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ref mut generator,
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} = c.resources;
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let digital_inputs = [
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digital_inputs.0.is_high().unwrap(),
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digital_inputs.1.is_high().unwrap(),
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];
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telemetry.digital_inputs = digital_inputs;
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let hold =
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settings.force_hold || (digital_inputs[1] && settings.allow_hold);
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(adc0, adc1, dac0, dac1).lock(|adc0, adc1, dac0, dac1| {
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let adc_samples = [adc0, adc1];
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let dac_samples = [dac0, dac1];
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// Preserve instruction and data ordering w.r.t. DMA flag access.
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fence(Ordering::SeqCst);
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for channel in 0..adc_samples.len() {
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adc_samples[channel]
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.iter()
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.zip(dac_samples[channel].iter_mut())
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.map(|(ai, di)| {
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let x = f32::from(*ai as i16);
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let y = settings.iir_ch[channel]
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.iter()
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.zip(iir_state[channel].iter_mut())
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.fold(x, |yi, (ch, state)| {
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ch.update(state, yi, hold)
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});
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// Note(unsafe): The filter limits must ensure that the value is in range.
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// The truncation introduces 1/2 LSB distortion.
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let y: i16 = unsafe { y.to_int_unchecked() };
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// Convert to DAC code
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*di = DacCode::from(y).0;
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})
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.last();
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}
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// Stream the data.
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generator.send(&adc_samples, &dac_samples);
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// Update telemetry measurements.
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telemetry.adcs =
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[AdcCode(adc_samples[0][0]), AdcCode(adc_samples[1][0])];
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telemetry.dacs =
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[DacCode(dac_samples[0][0]), DacCode(dac_samples[1][0])];
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// Preserve instruction and data ordering w.r.t. DMA flag access.
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fence(Ordering::SeqCst);
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});
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}
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#[idle(resources=[network], spawn=[settings_update])]
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fn idle(mut c: idle::Context) -> ! {
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loop {
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match c.resources.network.lock(|net| net.update()) {
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NetworkState::SettingsChanged => {
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c.spawn.settings_update().unwrap()
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}
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NetworkState::Updated => {}
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NetworkState::NoChange => cortex_m::asm::wfi(),
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}
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}
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}
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#[task(priority = 1, resources=[network, afes, settings])]
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fn settings_update(mut c: settings_update::Context) {
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// Update the IIR channels.
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let settings = c.resources.network.miniconf.settings();
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c.resources.settings.lock(|current| *current = *settings);
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// Update AFEs
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c.resources.afes.0.set_gain(settings.afe[0]);
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c.resources.afes.1.set_gain(settings.afe[1]);
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let target = settings.stream_target.into();
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c.resources.network.direct_stream(target);
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}
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#[task(priority = 1, resources=[network, settings, telemetry], schedule=[telemetry])]
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fn telemetry(mut c: telemetry::Context) {
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let telemetry: TelemetryBuffer =
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c.resources.telemetry.lock(|telemetry| *telemetry);
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let (gains, telemetry_period) = c
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.resources
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.settings
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.lock(|settings| (settings.afe, settings.telemetry_period));
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c.resources
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.network
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.telemetry
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.publish(&telemetry.finalize(gains[0], gains[1]));
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// Schedule the telemetry task in the future.
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c.schedule
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.telemetry(
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c.scheduled
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+ SystemTimer::ticks_from_secs(telemetry_period as u32),
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)
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.unwrap();
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}
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#[task(priority = 1, resources=[network], schedule=[ethernet_link])]
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fn ethernet_link(c: ethernet_link::Context) {
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c.resources.network.processor.handle_link();
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c.schedule
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.ethernet_link(c.scheduled + SystemTimer::ticks_from_secs(1))
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.unwrap();
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}
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#[task(binds = ETH, priority = 1)]
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fn eth(_: eth::Context) {
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unsafe { hal::ethernet::interrupt_handler() }
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}
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#[task(binds = SPI2, priority = 3)]
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fn spi2(_: spi2::Context) {
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panic!("ADC0 SPI error");
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}
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#[task(binds = SPI3, priority = 3)]
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fn spi3(_: spi3::Context) {
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panic!("ADC1 SPI error");
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}
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#[task(binds = SPI4, priority = 3)]
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fn spi4(_: spi4::Context) {
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panic!("DAC0 SPI error");
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}
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#[task(binds = SPI5, priority = 3)]
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fn spi5(_: spi5::Context) {
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panic!("DAC1 SPI error");
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}
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extern "C" {
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// hw interrupt handlers for RTIC to use for scheduling tasks
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// one per priority
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fn DCMI();
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fn JPEG();
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fn SDMMC();
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}
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};
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