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90bd4741cc
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dsp/benches: iir vec5
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2021-02-01 13:27:49 +01:00 |
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47089c267c
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dsp: align iir and iir_int, add iir micro benches
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2021-01-31 19:12:24 +01:00 |
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8408bc5811
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dsp/bench: add pll/rpll micro benches
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2021-01-31 18:54:09 +01:00 |
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eea5033d36
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dsp bench: fix
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2021-01-22 11:38:38 +01:00 |
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Matt Huszagh
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3125365a15
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add atan2 host benchmark
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2020-12-17 14:01:57 -08:00 |
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Matt Huszagh
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2ddaab8fae
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dsp: fix bench import path
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2020-12-16 16:57:18 -08:00 |
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Matt Huszagh
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7c4f608206
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move cossin and atan2 into the same trig file
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2020-12-16 16:26:44 -08:00 |
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d271dccaba
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cossin bench: be fair to glibc
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2020-12-11 19:08:11 +01:00 |
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d4fceea5d1
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cossin: bench against (i32 as f32).sin_cos()
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2020-12-11 17:26:50 +01:00 |
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5cd93d3318
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fmt
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2020-12-11 17:08:16 +01:00 |
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a85738a651
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dsp: add host benchmark
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2020-12-11 15:19:13 +01:00 |
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