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3abd47494b
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Fixing DMA2 instantiation issue
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2021-02-16 15:10:00 +01:00 |
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12ea66a3f7
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update cargosha256
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2021-02-16 11:45:44 +08:00 |
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cca8adb608
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Merge pull request #270 from quartiq/rj/deps
dependencies: bump
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2021-02-15 09:31:29 +01:00 |
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43c0ba9ea0
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dependencies: bump
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2021-02-15 09:18:31 +01:00 |
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fcf59be684
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Merge pull request #269 from quartiq/rj/misc
fix hal branch, cleanup code
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2021-02-15 09:00:58 +01:00 |
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efbf750b20
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Merge remote-tracking branch 'origin/master' into rj/misc
* origin/master:
Upgrade to serde-json-core v0.2.0
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2021-02-15 08:55:40 +01:00 |
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cfc4cb382d
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dependencies: hal ref is on master now [nfc]
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2021-02-15 08:53:55 +01:00 |
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5fc45a659b
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lockin-external: comment style [nfc]
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2021-02-15 08:51:19 +01:00 |
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a926c3554b
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Merge pull request #268 from dnadlinger/json-020
Upgrade to serde-json-core v0.2.0
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2021-02-15 08:04:44 +01:00 |
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b581a016ce
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lockin: redundant new
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2021-02-14 17:55:01 +01:00 |
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David Nadlinger
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4130292706
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Upgrade to serde-json-core v0.2.0
This also fixes the network interface for writing IIR coefficients.
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2021-02-13 00:07:15 +00:00 |
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16c986ab1b
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Merge pull request #267 from quartiq/rj/lowpass2
lowpass2
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2021-02-12 12:23:26 +01:00 |
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8918952b96
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complex: lint
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2021-02-12 12:06:00 +01:00 |
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71c6e52f4d
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complex: add some traits
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2021-02-12 12:03:53 +01:00 |
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a6d4099ed3
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lowpass: expose natural gain, add bias
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2021-02-12 11:06:59 +01:00 |
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67f052c0c9
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lockin: add rounding bias
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2021-02-12 11:05:50 +01:00 |
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32b7058b47
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lockin: 2nd order lowpass
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2021-02-11 23:15:32 +01:00 |
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b49f0a2eb9
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complex: log2, update bins
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2021-02-11 18:14:28 +01:00 |
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3ae0b710bc
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lowpass: reimplement better
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2021-02-11 14:30:05 +01:00 |
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c89f348f5e
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Merge pull request #266 from quartiq/rj/lowpass
new lowpass
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2021-02-10 14:25:46 +01:00 |
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a144c099b2
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lowpass: fmt
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2021-02-10 14:10:28 +01:00 |
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beeb43bf8b
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lowpass: robustify
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2021-02-10 13:44:10 +01:00 |
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8d68504026
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lowpass: symmetric code
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2021-02-10 13:31:41 +01:00 |
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13b47556fd
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lowpass: clippy
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2021-02-10 13:27:56 +01:00 |
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30c2c2aac2
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lowpass: i32, no multiplies
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2021-02-10 11:39:19 +01:00 |
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208ba8379a
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dsp, lockin: use cascaded 1st order lowpasses
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2021-02-09 20:37:46 +01:00 |
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ae43f60d60
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Merge pull request #263 from quartiq/rj/deglitch-misc
deglitch timer input, miscellaneous changes
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2021-02-09 15:39:24 +01:00 |
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03cbd99aee
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Merge pull request #265 from quartiq/rs/timer-input-filter-config
Adding support for input capture prefilter configuration
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2021-02-09 15:03:30 +01:00 |
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724768a72e
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Adding safety docs
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2021-02-09 14:37:49 +01:00 |
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2e358dea26
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Adding support for input capture prefilter configuration
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2021-02-09 14:36:50 +01:00 |
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31781a9d0e
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iir_int: rounding bias
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2021-02-09 12:17:48 +01:00 |
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611bd3e855
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ad9959/pounder: tweaks
* make a trait public
* use self-test
* this hasn't been tested
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2021-02-08 15:24:52 +01:00 |
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1b46f081c1
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better formatting
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2021-02-08 11:26:58 +01:00 |
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9b6ab29eb7
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update cargosha256
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2021-02-08 09:56:42 +08:00 |
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deed11f110
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lockin-external: simplify
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2021-02-05 18:59:22 +01:00 |
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47d8a74524
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ci: simplify nightly
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2021-02-04 17:01:18 +01:00 |
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0343e5d8ab
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pounder timer is u16
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2021-02-04 16:51:34 +01:00 |
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f19988a1bd
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up the sample rate
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2021-02-04 15:42:45 +01:00 |
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2d492055f3
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pounder stamper: overflow at u32 boundary
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2021-02-04 15:42:29 +01:00 |
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473bdaa9bc
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iir_int: use f64 for extreme filters
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2021-02-04 15:21:05 +01:00 |
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8314844aeb
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pounder: moved SAMPLE_BUFFER_SIZE
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2021-02-04 13:36:24 +01:00 |
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d32378e6c4
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lockin-external: ignore timestamps related to capture overflows
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2021-02-04 12:48:58 +01:00 |
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f47ee38d31
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move sample ticks and buffer size to design parameters
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2021-02-04 12:48:25 +01:00 |
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7ce90c4d31
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input stamper: add deglitching
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2021-02-04 12:47:35 +01:00 |
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f250e036ca
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rpll: simplify parameters, add one test
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2021-02-04 12:46:33 +01:00 |
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bors[bot]
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5951a0d41d
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Merge #262
262: core_intrinsics attr need to be in the lib crate r=jordens a=jordens
Co-authored-by: Robert Jördens <rj@quartiq.de>
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2021-02-03 17:15:46 +00:00 |
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4dfe16fce8
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ci: don't save binaries
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2021-02-03 18:14:42 +01:00 |
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1167c7693d
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bors: depend on test
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2021-02-03 18:01:24 +01:00 |
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4d37a5483f
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ci: add release automation
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2021-02-03 17:59:44 +01:00 |
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5c8f316160
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Update ci.yml
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2021-02-03 17:24:06 +01:00 |
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