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Merge branch 'feature/dma-updates' into feature/digital-input-stamp

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This commit is contained in:
Ryan Summers 2020-11-11 16:30:23 +01:00
commit d06a350549
9 changed files with 252 additions and 128 deletions
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9
.github/workflows/ci.yml vendored
View File

@ -2,10 +2,9 @@ name: Continuous Integration
on:
push:
branches:
- staging
- trying
- master
branches: [master, staging, trying]
pull_request:
branches: [master]
env:
CARGO_TERM_COLOR: always
@ -42,7 +41,7 @@ jobs:
uses: actions-rs/cargo@v1
continue-on-error: true
with:
command: clippy
command: clippy
compile:
runs-on: ubuntu-latest

74
Cargo.lock generated
View File

@ -344,37 +344,12 @@ dependencies = [
"cortex-m-semihosting",
]
[[package]]
name = "paste"
version = "0.1.18"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "45ca20c77d80be666aef2b45486da86238fabe33e38306bd3118fe4af33fa880"
dependencies = [
"paste-impl",
"proc-macro-hack",
]
[[package]]
name = "paste"
version = "1.0.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "ba7ae1a2180ed02ddfdb5ab70c70d596a26dd642e097bb6fe78b1bde8588ed97"
[[package]]
name = "paste-impl"
version = "0.1.18"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "d95a7db200b97ef370c8e6de0088252f7e0dfff7d047a28528e47456c0fc98b6"
dependencies = [
"proc-macro-hack",
]
[[package]]
name = "proc-macro-hack"
version = "0.5.19"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "dbf0c48bc1d91375ae5c3cd81e3722dff1abcf81a30960240640d223f59fe0e5"
[[package]]
name = "proc-macro2"
version = "1.0.24"
@ -478,7 +453,6 @@ checksum = "0fe46639fd2ec79eadf8fe719f237a7a0bd4dac5d957f1ca5bbdbc1c3c39e53a"
dependencies = [
"bitflags",
"byteorder",
"log",
"managed",
]
@ -503,8 +477,7 @@ dependencies = [
"serde",
"serde-json-core",
"smoltcp",
"stm32h7-ethernet",
"stm32h7xx-hal 0.8.0",
"stm32h7xx-hal",
]
[[package]]
@ -513,17 +486,6 @@ version = "1.2.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "a8f112729512f8e442d81f95a8a7ddf2b7c6b8a1a6f509a95864142b30cab2d3"
[[package]]
name = "stm32h7"
version = "0.11.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "e9beb5e2a223c82f263c3051bba4614aebc6e98bd40217df3cd8817c83ac7bd8"
dependencies = [
"bare-metal 0.2.5",
"cortex-m",
"vcell",
]
[[package]]
name = "stm32h7"
version = "0.12.1"
@ -536,38 +498,10 @@ dependencies = [
"vcell",
]
[[package]]
name = "stm32h7-ethernet"
version = "0.1.1"
source = "git+https://github.com/quartiq/stm32h7-ethernet.git#cf9b8bb2e1b440d8ada6ac6048f48dc4ed9c269a"
dependencies = [
"cortex-m",
"log",
"smoltcp",
"stm32h7xx-hal 0.5.0",
]
[[package]]
name = "stm32h7xx-hal"
version = "0.5.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "987c66628f30012ed9a41cc738421c5caece03292c0cc8fd1e99956f122735bd"
dependencies = [
"bare-metal 0.2.5",
"cast",
"cortex-m",
"cortex-m-rt",
"embedded-hal",
"nb 0.1.3",
"paste 0.1.18",
"stm32h7 0.11.0",
"void",
]
[[package]]
name = "stm32h7xx-hal"
version = "0.8.0"
source = "git+https://github.com/quartiq/stm32h7xx-hal?branch=feature/stabilizer-dma#8516690d4f35bc4bb184eba2ee8b48d4490ec85b"
source = "git+https://github.com/quartiq/stm32h7xx-hal?branch=feature/dma-rtic-example#d8cb6fa5099282665f5e5068a9dcdc9ebaa63240"
dependencies = [
"bare-metal 1.0.0",
"cast",
@ -576,9 +510,9 @@ dependencies = [
"embedded-dma",
"embedded-hal",
"nb 1.0.0",
"paste 1.0.2",
"paste",
"smoltcp",
"stm32h7 0.12.1",
"stm32h7",
"void",
]

9
Cargo.toml
View File

@ -52,15 +52,10 @@ default-features = false
[dependencies.ad9959]
path = "ad9959"
[dependencies.stm32h7-ethernet]
git = "https://github.com/quartiq/stm32h7-ethernet.git"
branch = "master"
features = ["stm32h743v"]
[dependencies.stm32h7xx-hal]
features = ["stm32h743v", "rt", "unproven", "ethernet", "quadspi"]
git = "https://github.com/quartiq/stm32h7xx-hal"
branch = "feature/stabilizer-dma"
branch = "feature/dma-rtic-example"
[features]
semihosting = ["panic-semihosting", "cortex-m-log/semihosting"]
@ -70,7 +65,7 @@ nightly = ["cortex-m/inline-asm"]
[profile.dev]
codegen-units = 1
incremental = false
opt-level = 1
opt-level = 3
[profile.release]
opt-level = 3

2
cargosha256.nix
View File

@ -1 +1 @@
"1626aw5ln581s1jzsf74y0djh715hdsjxzd3ck0xnb84a6kd4hkw"
"05b1xcr9jachnih0d6i63cfjcb88xrddmr2kf4h3vfwpjf8y9w10"

3
openocd.gdb
View File

@ -26,6 +26,3 @@ set var $t0=*$cc
continue
end
#set var $t0=*$cc
source ../../PyCortexMDebug/cmdebug/svd_gdb.py
svd_load ~/Downloads/STM32H743x.svd

167
src/adc.rs
View File

@ -1,13 +1,36 @@
///! Stabilizer ADC management interface
///!
///! The Stabilizer ADCs utilize a DMA channel to trigger sampling. The SPI streams are configured
///! for full-duplex operation, but only RX is connected to physical pins. A timer channel is
///! configured to generate a DMA write into the SPI TXFIFO, which initiates a SPI transfer and
///! results in an ADC sample read for both channels.
///!
///! In order to read multiple samples without interrupting the CPU, a separate DMA transfer is
///! configured to read from each of the ADC SPI RX FIFOs. Due to the design of the SPI peripheral,
///! these DMA transfers stall when no data is available in the FIFO. Thus, the DMA transfer only
///! completes after all samples have been read. When this occurs, a CPU interrupt is generated so
///! that software can process the acquired samples from both ADCs. Only one of the ADC DMA streams
///! is configured to generate an interrupt to handle both transfers, so it is necessary to ensure
///! both transfers are completed before reading the data. This is usually not significant for
///! busy-waiting because the transfers should complete at approximately the same time.
use super::{
hal, DMAReq, DmaConfig, MemoryToPeripheral, PeripheralToMemory, Priority,
Stream, TargetAddress, Transfer,
TargetAddress, Transfer,
};
// The desired ADC input buffer size. This is use configurable.
const INPUT_BUFFER_SIZE: usize = 1;
// The following data is written by the timer ADC sample trigger into each of the SPI TXFIFOs. Note
// that because the SPI MOSI line is not connected, this data is dont-care. Data in AXI SRAM is not
// initialized on boot, so the contents are random.
#[link_section = ".axisram.buffers"]
static mut SPI_START: [u16; 1] = [0x00];
// The following global buffers are used for the ADC sample DMA transfers. Two buffers are used for
// each transfer in a ping-pong buffer configuration (one is being acquired while the other is being
// processed). Note that the contents of AXI SRAM is uninitialized, so the buffer contents on
// startup are undefined.
#[link_section = ".axisram.buffers"]
static mut ADC0_BUF0: [u16; INPUT_BUFFER_SIZE] = [0; INPUT_BUFFER_SIZE];
@ -20,8 +43,9 @@ static mut ADC1_BUF0: [u16; INPUT_BUFFER_SIZE] = [0; INPUT_BUFFER_SIZE];
#[link_section = ".axisram.buffers"]
static mut ADC1_BUF1: [u16; INPUT_BUFFER_SIZE] = [0; INPUT_BUFFER_SIZE];
/// SPI2 is used as a ZST (zero-sized type) for indicating a DMA transfer into the SPI2 TX FIFO
/// whenever the tim2 update dma request occurs.
struct SPI2 {}
impl SPI2 {
pub fn new() -> Self {
Self {}
@ -29,18 +53,23 @@ impl SPI2 {
}
unsafe impl TargetAddress<MemoryToPeripheral> for SPI2 {
/// SPI2 is configured to operate using 16-bit transfer words.
type MemSize = u16;
const REQUEST_LINE: Option<u8> = Some(DMAReq::TIM2_UP as u8);
/// SPI2 DMA requests are generated whenever TIM2 CH1 comparison occurs.
const REQUEST_LINE: Option<u8> = Some(DMAReq::TIM2_CH1 as u8);
/// Whenever the DMA request occurs, it should write into SPI2's TX FIFO to start a DMA
/// transfer.
fn address(&self) -> u32 {
let regs = unsafe { &*hal::stm32::SPI2::ptr() };
&regs.txdr as *const _ as u32
}
}
/// SPI3 is used as a ZST (zero-sized type) for indicating a DMA transfer into the SPI3 TX FIFO
/// whenever the tim2 update dma request occurs.
struct SPI3 {}
impl SPI3 {
pub fn new() -> Self {
Self {}
@ -48,26 +77,37 @@ impl SPI3 {
}
unsafe impl TargetAddress<MemoryToPeripheral> for SPI3 {
/// SPI3 is configured to operate using 16-bit transfer words.
type MemSize = u16;
const REQUEST_LINE: Option<u8> = Some(DMAReq::TIM2_UP as u8);
/// SPI3 DMA requests are generated whenever TIM2 CH2 comparison occurs.
const REQUEST_LINE: Option<u8> = Some(DMAReq::TIM2_CH2 as u8);
/// Whenever the DMA request occurs, it should write into SPI3's TX FIFO to start a DMA
/// transfer.
fn address(&self) -> u32 {
let regs = unsafe { &*hal::stm32::SPI3::ptr() };
&regs.txdr as *const _ as u32
}
}
/// Represents both ADC input channels.
pub struct AdcInputs {
adc0: Adc0Input,
adc1: Adc1Input,
}
impl AdcInputs {
/// Construct the ADC inputs.
pub fn new(adc0: Adc0Input, adc1: Adc1Input) -> Self {
Self { adc0, adc1 }
}
/// Interrupt handler to handle when the sample collection DMA transfer completes.
///
/// # Returns
/// (adc0, adc1) where adcN is a reference to the collected ADC samples. Two array references
/// are returned - one for each ADC sample stream.
pub fn transfer_complete_handler(
&mut self,
) -> (&[u16; INPUT_BUFFER_SIZE], &[u16; INPUT_BUFFER_SIZE]) {
@ -77,6 +117,7 @@ impl AdcInputs {
}
}
/// Represents data associated with ADC0.
pub struct Adc0Input {
next_buffer: Option<&'static mut [u16; INPUT_BUFFER_SIZE]>,
transfer: Transfer<
@ -85,72 +126,113 @@ pub struct Adc0Input {
PeripheralToMemory,
&'static mut [u16; INPUT_BUFFER_SIZE],
>,
_trigger_transfer: Transfer<
hal::dma::dma::Stream0<hal::stm32::DMA1>,
SPI2,
MemoryToPeripheral,
&'static mut [u16; 1],
>,
}
impl Adc0Input {
/// Construct the ADC0 input channel.
///
/// # Args
/// * `spi` - The SPI interface used to communicate with the ADC.
/// * `trigger_stream` - The DMA stream used to trigger each ADC transfer by writing a word into
/// the SPI TX FIFO.
/// * `data_stream` - The DMA stream used to read samples received over SPI into a data buffer.
pub fn new(
spi: hal::spi::Spi<hal::stm32::SPI2, hal::spi::Enabled, u16>,
trigger_stream: hal::dma::dma::Stream0<hal::stm32::DMA1>,
data_stream: hal::dma::dma::Stream1<hal::stm32::DMA1>,
) -> Self {
// The trigger stream constantly writes to the TX FIFO using a static word (dont-care
// contents). Thus, neither the memory or peripheral address ever change. This is run in
// circular mode to be completed at every DMA request.
let trigger_config = DmaConfig::default()
.memory_increment(false)
.peripheral_increment(false)
.priority(Priority::High)
.circular_buffer(true);
// Construct the trigger stream to write from memory to the peripheral.
let mut trigger_transfer: Transfer<_, _, MemoryToPeripheral, _> =
Transfer::init(
trigger_stream,
&SPI2::new(),
SPI2::new(),
unsafe { &mut SPI_START },
None,
trigger_config,
);
// The data stream constantly reads from the SPI RX FIFO into a RAM buffer. The peripheral
// stalls reads of the SPI RX FIFO until data is available, so the DMA transfer completes
// after the requested number of samples have been collected. Note that only ADC1's data
// stream is used to trigger a transfer completion interrupt.
let data_config = DmaConfig::default()
.memory_increment(true)
.priority(Priority::VeryHigh)
.peripheral_increment(false);
// A SPI peripheral error interrupt is used to determine if the RX FIFO overflows. This
// indicates that samples were dropped due to excessive processing time in the main
// application (e.g. a second DMA transfer completes before the first was done with
// processing). This is used as a flow control indicator to guarantee that no ADC samples
// are lost.
let mut spi = spi.disable();
spi.listen(hal::spi::Event::Error);
// The data transfer is always a transfer of data from the peripheral to a RAM buffer.
let mut data_transfer: Transfer<_, _, PeripheralToMemory, _> =
Transfer::init(
data_stream,
&spi,
spi,
unsafe { &mut ADC0_BUF0 },
None,
data_config,
);
spi.enable_dma_rx();
spi.enable_dma_tx();
data_transfer.start(|spi| {
// Allow the SPI FIFOs to operate using only DMA data channels.
spi.enable_dma_rx();
spi.enable_dma_tx();
let spi = spi.enable();
spi.inner().cr1.modify(|_, w| w.cstart().started());
// Enable SPI and start it in infinite transaction mode.
spi.inner().cr1.modify(|_, w| w.spe().set_bit());
spi.inner().cr1.modify(|_, w| w.cstart().started());
});
data_transfer.start();
trigger_transfer.start();
trigger_transfer.start(|_| {});
Self {
next_buffer: unsafe { Some(&mut ADC0_BUF1) },
transfer: data_transfer,
_trigger_transfer: trigger_transfer,
}
}
/// Handle a transfer completion.
///
/// # Returns
/// A reference to the underlying buffer that has been filled with ADC samples.
pub fn transfer_complete_handler(&mut self) -> &[u16; INPUT_BUFFER_SIZE] {
let next_buffer = self.next_buffer.take().unwrap();
while hal::dma::dma::Stream1::<hal::stm32::DMA1>::is_enabled() {}
// Wait for the transfer to fully complete before continuing.
while self.transfer.get_transfer_complete_flag() == false {}
// Start the next transfer.
self.transfer.clear_interrupts();
let (prev_buffer, _) =
self.transfer.next_transfer(next_buffer).unwrap();
self.next_buffer.replace(prev_buffer);
self.next_buffer.as_ref().unwrap()
}
}
/// Represents the data input stream from ADC1
pub struct Adc1Input {
next_buffer: Option<&'static mut [u16; INPUT_BUFFER_SIZE]>,
transfer: Transfer<
@ -159,68 +241,107 @@ pub struct Adc1Input {
PeripheralToMemory,
&'static mut [u16; INPUT_BUFFER_SIZE],
>,
_trigger_transfer: Transfer<
hal::dma::dma::Stream2<hal::stm32::DMA1>,
SPI3,
MemoryToPeripheral,
&'static mut [u16; 1],
>,
}
impl Adc1Input {
/// Construct a new ADC1 input data stream.
///
/// # Args
/// * `spi` - The SPI interface connected to ADC1.
/// * `trigger_stream` - The DMA stream used to trigger ADC conversions on the SPI interface.
/// * `data_stream` - The DMA stream used to read ADC samples from the SPI RX FIFO.
pub fn new(
spi: hal::spi::Spi<hal::stm32::SPI3, hal::spi::Enabled, u16>,
trigger_stream: hal::dma::dma::Stream2<hal::stm32::DMA1>,
data_stream: hal::dma::dma::Stream3<hal::stm32::DMA1>,
) -> Self {
// The trigger stream constantly writes to the TX FIFO using a static word (dont-care
// contents). Thus, neither the memory or peripheral address ever change. This is run in
// circular mode to be completed at every DMA request.
let trigger_config = DmaConfig::default()
.memory_increment(false)
.peripheral_increment(false)
.priority(Priority::High)
.circular_buffer(true);
// Construct the trigger stream to write from memory to the peripheral.
let mut trigger_transfer: Transfer<_, _, MemoryToPeripheral, _> =
Transfer::init(
trigger_stream,
&SPI3::new(),
SPI3::new(),
unsafe { &mut SPI_START },
None,
trigger_config,
);
// The data stream constantly reads from the SPI RX FIFO into a RAM buffer. The peripheral
// stalls reads of the SPI RX FIFO until data is available, so the DMA transfer completes
// after the requested number of samples have been collected. Note that only ADC1's data
// stream is used to trigger a transfer completion interrupt.
let data_config = DmaConfig::default()
.memory_increment(true)
.transfer_complete_interrupt(true)
.priority(Priority::VeryHigh)
.peripheral_increment(false);
// A SPI peripheral error interrupt is used to determine if the RX FIFO overflows. This
// indicates that samples were dropped due to excessive processing time in the main
// application (e.g. a second DMA transfer completes before the first was done with
// processing). This is used as a flow control indicator to guarantee that no ADC samples
// are lost.
let mut spi = spi.disable();
spi.listen(hal::spi::Event::Error);
// The data transfer is always a transfer of data from the peripheral to a RAM buffer.
let mut data_transfer: Transfer<_, _, PeripheralToMemory, _> =
Transfer::init(
data_stream,
&spi,
spi,
unsafe { &mut ADC1_BUF0 },
None,
data_config,
);
spi.enable_dma_rx();
spi.enable_dma_tx();
data_transfer.start(|spi| {
// Allow the SPI FIFOs to operate using only DMA data channels.
spi.enable_dma_rx();
spi.enable_dma_tx();
let spi = spi.enable();
spi.inner().cr1.modify(|_, w| w.cstart().started());
// Enable SPI and start it in infinite transaction mode.
spi.inner().cr1.modify(|_, w| w.spe().set_bit());
spi.inner().cr1.modify(|_, w| w.cstart().started());
});
data_transfer.start();
trigger_transfer.start();
trigger_transfer.start(|_| {});
Self {
next_buffer: unsafe { Some(&mut ADC1_BUF1) },
transfer: data_transfer,
_trigger_transfer: trigger_transfer,
}
}
/// Handle a transfer completion.
///
/// # Returns
/// A reference to the underlying buffer that has been filled with ADC samples.
pub fn transfer_complete_handler(&mut self) -> &[u16; INPUT_BUFFER_SIZE] {
let next_buffer = self.next_buffer.take().unwrap();
while hal::dma::dma::Stream3::<hal::stm32::DMA1>::is_enabled() {}
// Wait for the transfer to fully complete before continuing.
while self.transfer.get_transfer_complete_flag() == false {}
// Start the next transfer.
self.transfer.clear_interrupts();
let (prev_buffer, _) =
self.transfer.next_transfer(next_buffer).unwrap();
self.next_buffer.replace(prev_buffer);
self.next_buffer.as_ref().unwrap()
}

58
src/dac.rs
View File

@ -1,21 +1,44 @@
///! Stabilizer DAC output control
///!
///! Stabilizer output DACs do not currently rely on DMA requests for generating output.
///! Instead, the DACs utilize an internal queue for storing output codes. A timer then periodically
///! generates an interrupt which triggers an update of the DACs via a write over SPI.
use super::hal;
use heapless::consts;
/// Controller structure for managing the DAC outputs.
pub struct DacOutputs {
dac0_spi: hal::spi::Spi<hal::stm32::SPI4, hal::spi::Enabled, u16>,
dac1_spi: hal::spi::Spi<hal::stm32::SPI5, hal::spi::Enabled, u16>,
outputs: heapless::spsc::Queue<(u16, u16), consts::U32>,
timer: hal::timer::Timer<hal::stm32::TIM3>,
// The queue is provided a default length of 32 updates, but this queue can be updated by the
// end user to be larger if necessary.
outputs: heapless::spsc::Queue<(u16, u16), consts::U32>,
}
impl DacOutputs {
/// Construct a new set of DAC output controls
///
/// # Args
/// * `dac0_spi` - The SPI interface to the DAC0 output.
/// * `dac1_spi` - The SPI interface to the DAC1 output.
/// * `timer` - The timer used to generate periodic events for updating the DACs.
pub fn new(
dac0_spi: hal::spi::Spi<hal::stm32::SPI4, hal::spi::Enabled, u16>,
dac1_spi: hal::spi::Spi<hal::stm32::SPI5, hal::spi::Enabled, u16>,
mut dac0_spi: hal::spi::Spi<hal::stm32::SPI4, hal::spi::Enabled, u16>,
mut dac1_spi: hal::spi::Spi<hal::stm32::SPI5, hal::spi::Enabled, u16>,
mut timer: hal::timer::Timer<hal::stm32::TIM3>,
) -> Self {
// Start the DAC SPI interfaces in infinite transaction mode. CS is configured in
// auto-suspend mode.
dac0_spi.inner().cr1.modify(|_, w| w.cstart().started());
dac1_spi.inner().cr1.modify(|_, w| w.cstart().started());
dac0_spi.listen(hal::spi::Event::Error);
dac1_spi.listen(hal::spi::Event::Error);
// Stop the timer and begin listening for timeouts. Timeouts will be used as a means to
// generate new DAC outputs.
timer.pause();
timer.reset_counter();
timer.clear_irq();
@ -29,11 +52,28 @@ impl DacOutputs {
}
}
/// Push a set of new DAC output codes to the internal queue.
///
/// # Note
/// The earlier DAC output codes will be generated within 1 update cycle of the codes. This is a
/// fixed latency currently.
///
/// This function will panic if too many codes are written.
///
/// # Args
/// * `dac0_value` - The value to enqueue for a DAC0 update.
/// * `dac1_value` - The value to enqueue for a DAC1 update.
pub fn push(&mut self, dac0_value: u16, dac1_value: u16) {
self.outputs.enqueue((dac0_value, dac1_value)).unwrap();
self.timer.resume();
}
/// Update the DAC codes with the next set of values in the internal queue.
///
/// # Note
/// This is intended to be called from the TIM3 update ISR.
///
/// If the last value in the queue is used, the timer is stopped.
pub fn update(&mut self) {
self.timer.clear_irq();
match self.outputs.dequeue() {
@ -46,7 +86,19 @@ impl DacOutputs {
};
}
/// Write immediate values to the DAC outputs.
///
/// # Note
/// The DACs will be updated as soon as the SPI transfer completes, which will be nominally
/// 320nS after this function call.
///
/// # Args
/// * `dac0_value` - The output code to write to DAC0.
/// * `dac1_value` - The output code to write to DAC1.
pub fn write(&mut self, dac0_value: u16, dac1_value: u16) {
// In order to optimize throughput and minimize latency, the DAC codes are written directly
// into the SPI TX FIFO. No error checking is conducted. Errors are handled via interrupts
// instead.
unsafe {
core::ptr::write_volatile(
&self.dac0_spi.inner().txdr as *const _ as *mut u16,

10
src/iir.rs
View File

@ -105,14 +105,4 @@ impl IIR {
xy[xy.len() / 2] = y0;
y0
}
pub fn update_from_adc_sample(
&mut self,
sample: u16,
state: &mut IIRState,
) -> u16 {
let x0 = f32::from(sample as i16);
let y0 = self.update(state, x0);
y0 as i16 as u16 ^ 0x8000
}
}

48
src/main.rs
View File

@ -1,3 +1,4 @@
#![deny(warnings)]
#![allow(clippy::missing_safety_doc)]
#![no_std]
#![no_main]
@ -38,12 +39,15 @@ use hal::{
dma::{
config::Priority,
dma::{DMAReq, DmaConfig},
traits::{Stream, TargetAddress},
traits::TargetAddress,
MemoryToPeripheral, PeripheralToMemory, Transfer,
},
ethernet::{self, PHY},
};
use smoltcp as net;
use smoltcp::iface::Routes;
use smoltcp::wire::Ipv4Address;
use heapless::{consts::*, String};
@ -91,6 +95,7 @@ mod build_info {
pub struct NetStorage {
ip_addrs: [net::wire::IpCidr; 1],
neighbor_cache: [Option<(net::wire::IpAddress, net::iface::Neighbor)>; 8],
routes_storage: [Option<(smoltcp::wire::IpCidr, smoltcp::iface::Route)>; 1],
}
static mut NET_STORE: NetStorage = NetStorage {
@ -100,6 +105,8 @@ static mut NET_STORE: NetStorage = NetStorage {
)],
neighbor_cache: [None; 8],
routes_storage: [None; 1],
};
const SCALE: f32 = ((1 << 15) - 1) as f32;
@ -702,6 +709,10 @@ const APP: () = {
24,
);
let default_v4_gw = Ipv4Address::new(10, 0, 16, 1);
let mut routes = Routes::new(&mut store.routes_storage[..]);
routes.add_default_ipv4_route(default_v4_gw).unwrap();
let neighbor_cache =
net::iface::NeighborCache::new(&mut store.neighbor_cache[..]);
@ -709,6 +720,7 @@ const APP: () = {
.ethernet_addr(mac_addr)
.neighbor_cache(neighbor_cache)
.ip_addrs(&mut store.ip_addrs[..])
.routes(routes)
.finalize();
(interface, lan8742a)
@ -731,8 +743,14 @@ const APP: () = {
&ccdr.clocks,
);
{
// Listen to the CH1 and CH2 comparison events. These channels should have a value of
// zero loaded into them, so the event should occur whenever the timer overflows. Note
// that we use channels instead of timer updates because each SPI DMA transfer needs a
// unique request line.
let t2_regs = unsafe { &*hal::stm32::TIM2::ptr() };
t2_regs.dier.modify(|_, w| w.ude().set_bit());
t2_regs
.dier
.modify(|_, w| w.cc1de().set_bit().cc2de().set_bit());
}
init::LateResources {
@ -772,11 +790,19 @@ const APP: () = {
c.resources.adcs.transfer_complete_handler();
for (adc0, adc1) in adc0_samples.iter().zip(adc1_samples.iter()) {
let result_adc0 = c.resources.iir_ch[0]
.update_from_adc_sample(*adc0, &mut c.resources.iir_state[0]);
let result_adc0 = {
let x0 = f32::from(*adc0 as i16);
let y0 = c.resources.iir_ch[0]
.update(&mut c.resources.iir_state[0], x0);
y0 as i16 as u16 ^ 0x8000
};
let result_adc1 = c.resources.iir_ch[1]
.update_from_adc_sample(*adc1, &mut c.resources.iir_state[1]);
let result_adc1 = {
let x1 = f32::from(*adc1 as i16);
let y1 = c.resources.iir_ch[1]
.update(&mut c.resources.iir_state[1], x1);
y1 as i16 as u16 ^ 0x8000
};
c.resources
.dacs
@ -982,6 +1008,16 @@ const APP: () = {
panic!("ADC0 input overrun");
}
#[task(binds = SPI4, priority = 1)]
fn spi4(_: spi4::Context) {
panic!("DAC0 output error");
}
#[task(binds = SPI5, priority = 1)]
fn spi5(_: spi5::Context) {
panic!("DAC1 output error");
}
extern "C" {
// hw interrupt handlers for RTIC to use for scheduling tasks
// one per priority