Adding functional baseline HAL conversion
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3962f7eb68
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5
Cargo.lock
generated
5
Cargo.lock
generated
@ -313,12 +313,13 @@ dependencies = [
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"embedded-hal 0.2.3 (registry+https://github.com/rust-lang/crates.io-index)",
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"heapless 0.5.4 (registry+https://github.com/rust-lang/crates.io-index)",
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"log 0.4.8 (registry+https://github.com/rust-lang/crates.io-index)",
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"nb 0.1.2 (registry+https://github.com/rust-lang/crates.io-index)",
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"panic-halt 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)",
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"panic-semihosting 0.5.3 (registry+https://github.com/rust-lang/crates.io-index)",
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"serde 1.0.106 (registry+https://github.com/rust-lang/crates.io-index)",
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"serde-json-core 0.1.0 (registry+https://github.com/rust-lang/crates.io-index)",
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"smoltcp 0.6.0 (registry+https://github.com/rust-lang/crates.io-index)",
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"stm32h7xx-hal 0.4.0 (git+https://github.com/quartiq/stm32h7xx-hal.git?branch=feature/quad-spi)",
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"stm32h7xx-hal 0.4.0",
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]
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[[package]]
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@ -340,7 +341,6 @@ dependencies = [
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[[package]]
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name = "stm32h7xx-hal"
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version = "0.4.0"
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source = "git+https://github.com/quartiq/stm32h7xx-hal.git?branch=feature/quad-spi#a65de87263d87d5a730d21b5ebeea4bb1886233a"
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dependencies = [
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"bare-metal 0.2.5 (registry+https://github.com/rust-lang/crates.io-index)",
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"cast 0.2.3 (registry+https://github.com/rust-lang/crates.io-index)",
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@ -431,7 +431,6 @@ dependencies = [
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"checksum smoltcp 0.6.0 (registry+https://github.com/rust-lang/crates.io-index)" = "0fe46639fd2ec79eadf8fe719f237a7a0bd4dac5d957f1ca5bbdbc1c3c39e53a"
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"checksum stable_deref_trait 1.1.1 (registry+https://github.com/rust-lang/crates.io-index)" = "dba1a27d3efae4351c8051072d619e3ade2820635c3958d826bfea39d59b54c8"
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"checksum stm32h7 0.10.0 (registry+https://github.com/rust-lang/crates.io-index)" = "e5b0045066e082648e8a7ab1dd45c92efa8d7bec2beedf72ac7b62563911f82a"
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"checksum stm32h7xx-hal 0.4.0 (git+https://github.com/quartiq/stm32h7xx-hal.git?branch=feature/quad-spi)" = "<none>"
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"checksum syn 1.0.17 (registry+https://github.com/rust-lang/crates.io-index)" = "0df0eb663f387145cab623dea85b09c2c5b4b0aef44e945d928e682fce71bb03"
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"checksum typenum 1.12.0 (registry+https://github.com/rust-lang/crates.io-index)" = "373c8a200f9e67a0c95e62a4f52fbf80c23b4381c05a17845531982fa99e6b33"
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"checksum unicode-xid 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)" = "826e7639553986605ec5979c7dd957c7895e93eabed50ab2ffa7f6128a75097c"
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@ -38,10 +38,12 @@ serde-json-core = "0.1"
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cortex-m-rtfm = "0.5"
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smoltcp = { version = "0.6", features = ["ethernet", "proto-ipv4", "socket-tcp"], default-features = false }
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embedded-hal = "0.2.3"
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nb = "0.1.2"
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[dependencies.stm32h7xx-hal]
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git = "https://github.com/quartiq/stm32h7xx-hal.git"
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branch = "feature/quad-spi"
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#git = "https://github.com/quartiq/stm32h7xx-hal.git"
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#branch = "feature/quad-spi"
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path = "../stm32h7xx-hal/"
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features = ["stm32h743v", "rt"]
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[features]
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@ -52,6 +54,7 @@ nightly = ["cortex-m/inline-asm"]
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[profile.dev]
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codegen-units = 1
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incremental = false
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opt-level = 3
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[profile.release]
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debug = true
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148
src/main.rs
148
src/main.rs
@ -27,8 +27,11 @@ extern crate panic_halt;
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#[macro_use]
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extern crate log;
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use nb;
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// use core::sync::atomic::{AtomicU32, AtomicBool, Ordering};
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use cortex_m_rt::exception;
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use cortex_m::asm;
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use stm32h7xx_hal as hal;
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use stm32h7xx_hal::{
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prelude::*,
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@ -162,11 +165,11 @@ const APP: () = {
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// Configure the SPI interfaces to the ADCs and DACs.
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let adc1_spi = {
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let spi_miso = gpiob.pb14.into_alternate_af5();
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let spi_sck = gpiob.pb10.into_alternate_af5();
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let spi_miso = gpiob.pb14.into_alternate_af5().set_speed(hal::gpio::Speed::VeryHigh);
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let spi_sck = gpiob.pb10.into_alternate_af5().set_speed(hal::gpio::Speed::VeryHigh);
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let _spi_nss = gpiob.pb9.into_alternate_af5();
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let _config = hal::spi::Config::new(hal::spi::Mode{
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let config = hal::spi::Config::new(hal::spi::Mode{
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polarity: hal::spi::Polarity::IdleHigh,
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phase: hal::spi::Phase::CaptureOnSecondTransition,
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})
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@ -177,8 +180,8 @@ const APP: () = {
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let mut spi = dp.SPI2.spi(
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(spi_sck, spi_miso, hal::spi::NoMosi),
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hal::spi::MODE_0, //config,
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25.mhz(),
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config,
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50.mhz(),
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&clocks);
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spi.listen(hal::spi::Event::Rxp);
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@ -187,8 +190,8 @@ const APP: () = {
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};
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let adc2_spi = {
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let spi_miso = gpiob.pb4.into_alternate_af6();
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let spi_sck = gpioc.pc10.into_alternate_af6();
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let spi_miso = gpiob.pb4.into_alternate_af6().set_speed(hal::gpio::Speed::VeryHigh);
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let spi_sck = gpioc.pc10.into_alternate_af6().set_speed(hal::gpio::Speed::VeryHigh);
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let _spi_nss = gpioa.pa15.into_alternate_af6();
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@ -201,14 +204,12 @@ const APP: () = {
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.frame_size(16)
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.cs_delay(220e-9);
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let mut spi = dp.SPI3.spi(
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let spi = dp.SPI3.spi(
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(spi_sck, spi_miso, hal::spi::NoMosi),
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config,
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25.mhz(),
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50.mhz(),
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&clocks);
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spi.listen(hal::spi::Event::Rxp);
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spi
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};
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@ -308,9 +309,6 @@ const APP: () = {
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cp.SCB.enable_icache();
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// The cycle counter is used for RTFM scheduling.
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//cp.DWT.enable_cycle_counter();
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init_log();
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// info!("Version {} {}", build_info::PKG_VERSION, build_info::GIT_VERSION.unwrap());
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// info!("Built on {}", build_info::BUILT_TIME_UTC);
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@ -323,9 +321,7 @@ const APP: () = {
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dac_pin.set_low().unwrap();
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// Configure timer 2 to trigger conversions for the ADC
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let mut timer2 = dp.TIM2.timer(1.khz(), &mut clocks);
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timer2.clear_uif_bit();
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let mut timer2 = dp.TIM2.timer(500.khz(), &mut clocks);
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timer2.listen(hal::timer::Event::TimeOut);
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init::LateResources {
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@ -347,10 +343,55 @@ const APP: () = {
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}
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}
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#[task(binds = TIM2, resources = [dbg_pin, timer, adc1, adc2])]
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fn tim2(mut c: tim2::Context) {
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c.resources.timer.clear_uif_bit();
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c.resources.dbg_pin.set_high().unwrap();
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// Start a SPI transaction on ADC0 and ADC1
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c.resources.adc1.lock(|adc| adc.spi.cr1.modify(|_, w| w.cstart().set_bit()));
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c.resources.adc2.lock(|adc| adc.spi.cr1.modify(|_, w| w.cstart().set_bit()));
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c.resources.dbg_pin.set_low().unwrap();
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}
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#[task(binds = SPI2, resources = [adc1, dac1, adc2, dac2, iir_state, iir_ch, dac_pin], priority = 2)]
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fn adc_spi(c: spi2::Context) {
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#[cfg(feature = "bkpt")]
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cortex_m::asm::bkpt();
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c.resources.dac_pin.set_high().unwrap();
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let output_ch1 = {
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let a: u16 = c.resources.adc1.read().unwrap();
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let x0 = f32::from(a as i16);
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let y0 = c.resources.iir_ch[0].update(&mut c.resources.iir_state[0], x0);
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y0 as i16 as u16 ^ 0x8000
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};
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c.resources.adc1.spi.ifcr.write(|w| w.eotc().set_bit());
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let output_ch2 = {
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let a: u16 = nb::block!(c.resources.adc2.read()).unwrap();
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let x0 = f32::from(a as i16);
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let y0 = c.resources.iir_ch[1].update(&mut c.resources.iir_state[1], x0);
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y0 as i16 as u16 ^ 0x8000
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};
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c.resources.adc2.spi.ifcr.write(|w| w.eotc().set_bit());
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c.resources.dac1.send(output_ch1).unwrap();
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c.resources.dac2.send(output_ch2).unwrap();
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c.resources.dac_pin.set_low().unwrap();
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#[cfg(feature = "bkpt")]
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cortex_m::asm::bkpt();
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}
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#[idle]
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fn idle(_c: idle::Context) -> ! {
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// TODO Implement and poll ethernet interface.
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loop {}
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loop {
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asm::nop();
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}
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}
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/*
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@ -456,77 +497,6 @@ const APP: () = {
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}
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*/
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#[task(binds = TIM2, resources = [dbg_pin, timer, adc1, adc2])]
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fn tim2(mut c: tim2::Context) {
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c.resources.timer.clear_uif_bit();
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c.resources.dbg_pin.set_high().unwrap();
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c.resources.dbg_pin.set_low().unwrap();
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c.resources.dbg_pin.set_high().unwrap();
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c.resources.dbg_pin.set_low().unwrap();
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// Start a SPI transaction on ADC0 and ADC1
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// TODO: Stagger these requests.
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c.resources.adc1.lock(|adc| adc.spi.cr1.modify(|_, w| w.cstart().set_bit()));
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c.resources.adc2.lock(|adc| adc.spi.cr1.modify(|_, w| w.cstart().set_bit()));
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}
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// seems to slow it down
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// #[link_section = ".data.spi1"]
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#[task(binds = SPI2, resources = [adc1, dac1, iir_state, iir_ch], priority = 2)]
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fn spi2(c: spi2::Context) {
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#[cfg(feature = "bkpt")]
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cortex_m::asm::bkpt();
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let adc = c.resources.adc1;
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let dac = c.resources.dac1;
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let iir_ch = c.resources.iir_ch;
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let iir_state = c.resources.iir_state;
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// TODO: Doesn't make sense if RXP is unset.
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if adc.is_rxp() {
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let a: u16 = adc.read().unwrap();
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let x0 = f32::from(a as i16);
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let y0 = iir_ch[0].update(&mut iir_state[0], x0);
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let d = y0 as i16 as u16 ^ 0x8000;
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// TODO: Handle errors.
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dac.send(d).unwrap();
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}
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adc.spi.ifcr.write(|w| w.eotc().set_bit());
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#[cfg(feature = "bkpt")]
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cortex_m::asm::bkpt();
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}
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#[task(binds = SPI3, resources = [adc2, dac2, iir_state, iir_ch, dac_pin], priority = 2)]
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fn spi3(c: spi3::Context) {
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#[cfg(feature = "bkpt")]
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cortex_m::asm::bkpt();
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let adc = c.resources.adc2;
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let dac = c.resources.dac2;
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let iir_ch = c.resources.iir_ch;
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let iir_state = c.resources.iir_state;
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c.resources.dac_pin.set_high().unwrap();
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// TODO: Doesn't make sense if RXP is unset.
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if adc.is_rxp() {
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let a: u16 = adc.read().unwrap();
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let x0 = f32::from(a as i16);
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let y0 = iir_ch[1].update(&mut iir_state[1], x0);
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let d = y0 as i16 as u16 ^ 0x8000;
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// TODO: Handle errors.
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dac.send(d).unwrap();
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}
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adc.spi.ifcr.write(|w| w.eotc().set_bit());
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c.resources.dac_pin.set_low().unwrap();
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#[cfg(feature = "bkpt")]
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cortex_m::asm::bkpt();
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}
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/*
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#[task(binds = ETH, resources = [ethernet_periph], priority = 1)]
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fn eth(c: eth::Context) {
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