diff --git a/Cargo.lock b/Cargo.lock
index 7b47d33..829e231 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -313,12 +313,13 @@ dependencies = [
  "embedded-hal 0.2.3 (registry+https://github.com/rust-lang/crates.io-index)",
  "heapless 0.5.4 (registry+https://github.com/rust-lang/crates.io-index)",
  "log 0.4.8 (registry+https://github.com/rust-lang/crates.io-index)",
+ "nb 0.1.2 (registry+https://github.com/rust-lang/crates.io-index)",
  "panic-halt 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)",
  "panic-semihosting 0.5.3 (registry+https://github.com/rust-lang/crates.io-index)",
  "serde 1.0.106 (registry+https://github.com/rust-lang/crates.io-index)",
  "serde-json-core 0.1.0 (registry+https://github.com/rust-lang/crates.io-index)",
  "smoltcp 0.6.0 (registry+https://github.com/rust-lang/crates.io-index)",
- "stm32h7xx-hal 0.4.0 (git+https://github.com/quartiq/stm32h7xx-hal.git?branch=feature/quad-spi)",
+ "stm32h7xx-hal 0.4.0",
 ]
 
 [[package]]
@@ -340,7 +341,6 @@ dependencies = [
 [[package]]
 name = "stm32h7xx-hal"
 version = "0.4.0"
-source = "git+https://github.com/quartiq/stm32h7xx-hal.git?branch=feature/quad-spi#a65de87263d87d5a730d21b5ebeea4bb1886233a"
 dependencies = [
  "bare-metal 0.2.5 (registry+https://github.com/rust-lang/crates.io-index)",
  "cast 0.2.3 (registry+https://github.com/rust-lang/crates.io-index)",
@@ -431,7 +431,6 @@ dependencies = [
 "checksum smoltcp 0.6.0 (registry+https://github.com/rust-lang/crates.io-index)" = "0fe46639fd2ec79eadf8fe719f237a7a0bd4dac5d957f1ca5bbdbc1c3c39e53a"
 "checksum stable_deref_trait 1.1.1 (registry+https://github.com/rust-lang/crates.io-index)" = "dba1a27d3efae4351c8051072d619e3ade2820635c3958d826bfea39d59b54c8"
 "checksum stm32h7 0.10.0 (registry+https://github.com/rust-lang/crates.io-index)" = "e5b0045066e082648e8a7ab1dd45c92efa8d7bec2beedf72ac7b62563911f82a"
-"checksum stm32h7xx-hal 0.4.0 (git+https://github.com/quartiq/stm32h7xx-hal.git?branch=feature/quad-spi)" = "<none>"
 "checksum syn 1.0.17 (registry+https://github.com/rust-lang/crates.io-index)" = "0df0eb663f387145cab623dea85b09c2c5b4b0aef44e945d928e682fce71bb03"
 "checksum typenum 1.12.0 (registry+https://github.com/rust-lang/crates.io-index)" = "373c8a200f9e67a0c95e62a4f52fbf80c23b4381c05a17845531982fa99e6b33"
 "checksum unicode-xid 0.2.0 (registry+https://github.com/rust-lang/crates.io-index)" = "826e7639553986605ec5979c7dd957c7895e93eabed50ab2ffa7f6128a75097c"
diff --git a/Cargo.toml b/Cargo.toml
index 87e1ffe..209a2b9 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -38,10 +38,12 @@ serde-json-core = "0.1"
 cortex-m-rtfm = "0.5"
 smoltcp = { version = "0.6", features = ["ethernet", "proto-ipv4", "socket-tcp"], default-features = false }
 embedded-hal = "0.2.3"
+nb = "0.1.2"
 
 [dependencies.stm32h7xx-hal]
-git = "https://github.com/quartiq/stm32h7xx-hal.git"
-branch = "feature/quad-spi"
+#git = "https://github.com/quartiq/stm32h7xx-hal.git"
+#branch = "feature/quad-spi"
+path = "../stm32h7xx-hal/"
 features = ["stm32h743v", "rt"]
 
 [features]
@@ -52,6 +54,7 @@ nightly = ["cortex-m/inline-asm"]
 [profile.dev]
 codegen-units = 1
 incremental = false
+opt-level = 3
 
 [profile.release]
 debug = true
diff --git a/src/main.rs b/src/main.rs
index 601c369..c9d3098 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -27,8 +27,11 @@ extern crate panic_halt;
 #[macro_use]
 extern crate log;
 
+use nb;
+
 // use core::sync::atomic::{AtomicU32, AtomicBool, Ordering};
 use cortex_m_rt::exception;
+use cortex_m::asm;
 use stm32h7xx_hal as hal;
 use stm32h7xx_hal::{
     prelude::*,
@@ -162,11 +165,11 @@ const APP: () = {
 
         // Configure the SPI interfaces to the ADCs and DACs.
         let adc1_spi = {
-            let spi_miso = gpiob.pb14.into_alternate_af5();
-            let spi_sck = gpiob.pb10.into_alternate_af5();
+            let spi_miso = gpiob.pb14.into_alternate_af5().set_speed(hal::gpio::Speed::VeryHigh);
+            let spi_sck = gpiob.pb10.into_alternate_af5().set_speed(hal::gpio::Speed::VeryHigh);
             let _spi_nss = gpiob.pb9.into_alternate_af5();
 
-            let _config = hal::spi::Config::new(hal::spi::Mode{
+            let config = hal::spi::Config::new(hal::spi::Mode{
                     polarity: hal::spi::Polarity::IdleHigh,
                     phase: hal::spi::Phase::CaptureOnSecondTransition,
                 })
@@ -177,8 +180,8 @@ const APP: () = {
 
             let mut spi = dp.SPI2.spi(
                     (spi_sck, spi_miso, hal::spi::NoMosi),
-                    hal::spi::MODE_0, //config,
-                    25.mhz(),
+                    config,
+                    50.mhz(),
                     &clocks);
 
             spi.listen(hal::spi::Event::Rxp);
@@ -187,8 +190,8 @@ const APP: () = {
         };
 
         let adc2_spi = {
-            let spi_miso = gpiob.pb4.into_alternate_af6();
-            let spi_sck = gpioc.pc10.into_alternate_af6();
+            let spi_miso = gpiob.pb4.into_alternate_af6().set_speed(hal::gpio::Speed::VeryHigh);
+            let spi_sck = gpioc.pc10.into_alternate_af6().set_speed(hal::gpio::Speed::VeryHigh);
             let _spi_nss = gpioa.pa15.into_alternate_af6();
 
 
@@ -201,14 +204,12 @@ const APP: () = {
                 .frame_size(16)
                 .cs_delay(220e-9);
 
-            let mut spi = dp.SPI3.spi(
+            let spi = dp.SPI3.spi(
                     (spi_sck, spi_miso, hal::spi::NoMosi),
                     config,
-                    25.mhz(),
+                    50.mhz(),
                     &clocks);
 
-            spi.listen(hal::spi::Event::Rxp);
-
             spi
         };
 
@@ -308,9 +309,6 @@ const APP: () = {
 
         cp.SCB.enable_icache();
 
-        // The cycle counter is used for RTFM scheduling.
-        //cp.DWT.enable_cycle_counter();
-
         init_log();
         // info!("Version {} {}", build_info::PKG_VERSION, build_info::GIT_VERSION.unwrap());
         // info!("Built on {}", build_info::BUILT_TIME_UTC);
@@ -323,9 +321,7 @@ const APP: () = {
         dac_pin.set_low().unwrap();
 
         // Configure timer 2 to trigger conversions for the ADC
-        let mut timer2 = dp.TIM2.timer(1.khz(), &mut clocks);
-        timer2.clear_uif_bit();
-
+        let mut timer2 = dp.TIM2.timer(500.khz(), &mut clocks);
         timer2.listen(hal::timer::Event::TimeOut);
 
         init::LateResources {
@@ -347,10 +343,55 @@ const APP: () = {
         }
     }
 
+    #[task(binds = TIM2, resources = [dbg_pin, timer, adc1, adc2])]
+    fn tim2(mut c: tim2::Context) {
+        c.resources.timer.clear_uif_bit();
+        c.resources.dbg_pin.set_high().unwrap();
+
+        // Start a SPI transaction on ADC0 and ADC1
+        c.resources.adc1.lock(|adc| adc.spi.cr1.modify(|_, w| w.cstart().set_bit()));
+        c.resources.adc2.lock(|adc| adc.spi.cr1.modify(|_, w| w.cstart().set_bit()));
+
+        c.resources.dbg_pin.set_low().unwrap();
+    }
+
+    #[task(binds = SPI2, resources = [adc1, dac1, adc2, dac2, iir_state, iir_ch, dac_pin], priority = 2)]
+    fn adc_spi(c: spi2::Context) {
+        #[cfg(feature = "bkpt")]
+        cortex_m::asm::bkpt();
+
+        c.resources.dac_pin.set_high().unwrap();
+
+        let output_ch1 = {
+            let a: u16 = c.resources.adc1.read().unwrap();
+            let x0 = f32::from(a as i16);
+            let y0 = c.resources.iir_ch[0].update(&mut c.resources.iir_state[0], x0);
+            y0 as i16 as u16 ^ 0x8000
+        };
+        c.resources.adc1.spi.ifcr.write(|w| w.eotc().set_bit());
+
+        let output_ch2 = {
+            let a: u16 = nb::block!(c.resources.adc2.read()).unwrap();
+            let x0 = f32::from(a as i16);
+            let y0 = c.resources.iir_ch[1].update(&mut c.resources.iir_state[1], x0);
+            y0 as i16 as u16 ^ 0x8000
+        };
+        c.resources.adc2.spi.ifcr.write(|w| w.eotc().set_bit());
+
+        c.resources.dac1.send(output_ch1).unwrap();
+        c.resources.dac2.send(output_ch2).unwrap();
+
+        c.resources.dac_pin.set_low().unwrap();
+        #[cfg(feature = "bkpt")]
+        cortex_m::asm::bkpt();
+    }
+
     #[idle]
     fn idle(_c: idle::Context) -> ! {
         // TODO Implement and poll ethernet interface.
-        loop {}
+        loop {
+            asm::nop();
+        }
     }
 
     /*
@@ -456,77 +497,6 @@ const APP: () = {
     }
     */
 
-    #[task(binds = TIM2, resources = [dbg_pin, timer, adc1, adc2])]
-    fn tim2(mut c: tim2::Context) {
-        c.resources.timer.clear_uif_bit();
-
-        c.resources.dbg_pin.set_high().unwrap();
-        c.resources.dbg_pin.set_low().unwrap();
-        c.resources.dbg_pin.set_high().unwrap();
-        c.resources.dbg_pin.set_low().unwrap();
-
-        // Start a SPI transaction on ADC0 and ADC1
-        // TODO: Stagger these requests.
-        c.resources.adc1.lock(|adc| adc.spi.cr1.modify(|_, w| w.cstart().set_bit()));
-        c.resources.adc2.lock(|adc| adc.spi.cr1.modify(|_, w| w.cstart().set_bit()));
-    }
-
-    // seems to slow it down
-    // #[link_section = ".data.spi1"]
-    #[task(binds = SPI2, resources = [adc1, dac1, iir_state, iir_ch], priority = 2)]
-    fn spi2(c: spi2::Context) {
-        #[cfg(feature = "bkpt")]
-        cortex_m::asm::bkpt();
-        let adc = c.resources.adc1;
-        let dac = c.resources.dac1;
-        let iir_ch = c.resources.iir_ch;
-        let iir_state = c.resources.iir_state;
-
-        // TODO: Doesn't make sense if RXP is unset.
-        if adc.is_rxp() {
-            let a: u16 = adc.read().unwrap();
-
-            let x0 = f32::from(a as i16);
-            let y0 = iir_ch[0].update(&mut iir_state[0], x0);
-            let d = y0 as i16 as u16 ^ 0x8000;
-
-            // TODO: Handle errors.
-            dac.send(d).unwrap();
-        }
-
-        adc.spi.ifcr.write(|w| w.eotc().set_bit());
-        #[cfg(feature = "bkpt")]
-        cortex_m::asm::bkpt();
-    }
-
-    #[task(binds = SPI3, resources = [adc2, dac2, iir_state, iir_ch, dac_pin], priority = 2)]
-    fn spi3(c: spi3::Context) {
-        #[cfg(feature = "bkpt")]
-        cortex_m::asm::bkpt();
-        let adc = c.resources.adc2;
-        let dac = c.resources.dac2;
-        let iir_ch = c.resources.iir_ch;
-        let iir_state = c.resources.iir_state;
-        c.resources.dac_pin.set_high().unwrap();
-
-        // TODO: Doesn't make sense if RXP is unset.
-        if adc.is_rxp() {
-            let a: u16 = adc.read().unwrap();
-
-            let x0 = f32::from(a as i16);
-            let y0 = iir_ch[1].update(&mut iir_state[1], x0);
-            let d = y0 as i16 as u16 ^ 0x8000;
-
-            // TODO: Handle errors.
-            dac.send(d).unwrap();
-        }
-        adc.spi.ifcr.write(|w| w.eotc().set_bit());
-
-        c.resources.dac_pin.set_low().unwrap();
-        #[cfg(feature = "bkpt")]
-        cortex_m::asm::bkpt();
-    }
-
     /*
     #[task(binds = ETH, resources = [ethernet_periph], priority = 1)]
     fn eth(c: eth::Context) {