Merge #352
352: Refactoring lockin binaries r=ryan-summers a=ryan-summers This PR merges `lockin-external` and `lockin-internal` into a single binary. This has also refactored the output configuration to make it more configurable. This was needed to work well with the reference signal generation, as that output should necessarily just override a different setting. Co-authored-by: Ryan Summers <ryan.summers@vertigo-designs.com> Co-authored-by: Robert Jördens <rj@quartiq.de>master
bors[bot]
GitHub
commit
bde0b0a4be
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@ -24,8 +24,7 @@ jobs:
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- run: >
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zip bin.zip
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target/*/release/dual-iir
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target/*/release/lockin-external
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target/*/release/lockin-internal
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target/*/release/lockin
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- id: create_release
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uses: actions/create-release@v1
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env:
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@ -29,9 +29,7 @@ to implement different use cases. Several applications are provides by default
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* anti-windup
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* derivative kick avoidance
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### Lockin external
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### Lockin internal
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### Lockin
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## Minimal bootstrapping documentation
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@ -1,143 +0,0 @@
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#![deny(warnings)]
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#![no_std]
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#![no_main]
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use dsp::{Accu, Complex, ComplexExt, Lockin};
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use generic_array::typenum::U2;
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use hardware::{Adc1Input, Dac0Output, Dac1Output, AFE0, AFE1};
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use stabilizer::{hardware, hardware::design_parameters};
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// A constant sinusoid to send on the DAC output.
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// Full-scale gives a +/- 10V amplitude waveform. Scale it down to give +/- 1V.
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const ONE: i16 = (0.1 * u16::MAX as f32) as _;
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const SQRT2: i16 = (ONE as f32 * 0.707) as _;
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const DAC_SEQUENCE: [i16; design_parameters::SAMPLE_BUFFER_SIZE] =
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[ONE, SQRT2, 0, -SQRT2, -ONE, -SQRT2, 0, SQRT2];
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#[rtic::app(device = stm32h7xx_hal::stm32, peripherals = true, monotonic = rtic::cyccnt::CYCCNT)]
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const APP: () = {
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struct Resources {
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afes: (AFE0, AFE1),
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adc: Adc1Input,
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dacs: (Dac0Output, Dac1Output),
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lockin: Lockin<U2>,
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}
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#[init]
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fn init(c: init::Context) -> init::LateResources {
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// Configure the microcontroller
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let (mut stabilizer, _pounder) = hardware::setup(c.core, c.device);
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// Enable ADC/DAC events
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stabilizer.adcs.1.start();
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stabilizer.dacs.0.start();
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stabilizer.dacs.1.start();
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// Start sampling ADCs.
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stabilizer.adc_dac_timer.start();
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init::LateResources {
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lockin: Lockin::default(),
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afes: stabilizer.afes,
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adc: stabilizer.adcs.1,
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dacs: stabilizer.dacs,
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}
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}
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/// Main DSP processing routine.
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///
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/// See `dual-iir` for general notes on processing time and timing.
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///
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/// This is an implementation of an internal-reference lockin on the ADC1 signal.
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/// The reference at f_sample/8 is output on DAC0 and the phase of the demodulated
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/// signal on DAC1.
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#[task(binds=DMA1_STR4, resources=[adc, dacs, lockin], priority=2)]
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fn process(c: process::Context) {
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let lockin = c.resources.lockin;
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let adc_samples = c.resources.adc.acquire_buffer();
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let dac_samples = [
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c.resources.dacs.0.acquire_buffer(),
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c.resources.dacs.1.acquire_buffer(),
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];
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// Reference phase and frequency are known.
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let pll_phase = 0i32;
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let pll_frequency =
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1i32 << (32 - design_parameters::SAMPLE_BUFFER_SIZE_LOG2);
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// Harmonic index of the LO: -1 to _de_modulate the fundamental (complex conjugate)
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let harmonic: i32 = -1;
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// Demodulation LO phase offset
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let phase_offset: i32 = 1 << 30;
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// Log2 lowpass time constant.
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let time_constant: u8 = 8;
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let sample_frequency = (pll_frequency as i32).wrapping_mul(harmonic);
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let sample_phase =
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phase_offset.wrapping_add(pll_phase.wrapping_mul(harmonic));
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let output: Complex<i32> = adc_samples
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.iter()
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// Zip in the LO phase.
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.zip(Accu::new(sample_phase, sample_frequency))
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// Convert to signed, MSB align the ADC sample, update the Lockin (demodulate, filter)
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.map(|(&sample, phase)| {
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let s = (sample as i16 as i32) << 16;
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lockin.update(s, phase, time_constant)
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})
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// Decimate
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.last()
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.unwrap()
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* 2; // Full scale assuming the 2f component is gone.
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// Convert to DAC data.
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for (i, data) in DAC_SEQUENCE.iter().enumerate() {
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// DAC0 always generates a fixed sinusoidal output.
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dac_samples[0][i] = *data as u16 ^ 0x8000;
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dac_samples[1][i] = (output.arg() >> 16) as u16 ^ 0x8000;
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}
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}
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#[idle(resources=[afes])]
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fn idle(_: idle::Context) -> ! {
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loop {
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cortex_m::asm::wfi();
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}
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}
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#[task(binds = ETH, priority = 1)]
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fn eth(_: eth::Context) {
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unsafe { stm32h7xx_hal::ethernet::interrupt_handler() }
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}
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#[task(binds = SPI2, priority = 3)]
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fn spi2(_: spi2::Context) {
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panic!("ADC0 input overrun");
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}
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#[task(binds = SPI3, priority = 3)]
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fn spi3(_: spi3::Context) {
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panic!("ADC1 input overrun");
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}
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#[task(binds = SPI4, priority = 3)]
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fn spi4(_: spi4::Context) {
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panic!("DAC0 output error");
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}
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#[task(binds = SPI5, priority = 3)]
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fn spi5(_: spi5::Context) {
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panic!("DAC1 output error");
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}
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extern "C" {
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// hw interrupt handlers for RTIC to use for scheduling tasks
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// one per priority
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fn DCMI();
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fn JPEG();
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fn SDMMC();
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}
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};
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@ -18,16 +18,34 @@ use stabilizer::hardware::{
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use miniconf::Miniconf;
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use stabilizer::net::{Action, MqttInterface};
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// A constant sinusoid to send on the DAC output.
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// Full-scale gives a +/- 10.24V amplitude waveform. Scale it down to give +/- 1V.
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const ONE: i16 = ((1.0 / 10.24) * i16::MAX as f32) as _;
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const SQRT2: i16 = (ONE as f32 * 0.707) as _;
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const DAC_SEQUENCE: [i16; design_parameters::SAMPLE_BUFFER_SIZE] =
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[ONE, SQRT2, 0, -SQRT2, -ONE, -SQRT2, 0, SQRT2];
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#[derive(Copy, Clone, Debug, Deserialize, Miniconf)]
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enum Conf {
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PowerPhase,
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FrequencyDiscriminator,
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Magnitude,
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Phase,
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ReferenceFrequency,
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LogPower,
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InPhase,
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Quadrature,
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Modulation,
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}
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#[derive(Copy, Clone, Debug, Miniconf, Deserialize, PartialEq)]
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enum LockinMode {
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Internal,
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External,
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}
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#[derive(Copy, Clone, Debug, Deserialize, Miniconf)]
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pub struct Settings {
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afe: [AfeGain; 2],
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lockin_mode: LockinMode,
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pll_tc: [u8; 2],
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@ -43,13 +61,15 @@ impl Default for Settings {
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Self {
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afe: [AfeGain::G1; 2],
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lockin_mode: LockinMode::External,
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pll_tc: [21, 21], // frequency and phase settling time (log2 counter cycles)
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lockin_tc: 6, // lockin lowpass time constant
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lockin_harmonic: -1, // Harmonic index of the LO: -1 to _de_modulate the fundamental (complex conjugate)
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lockin_phase: 0, // Demodulation LO phase offset
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output_conf: [Conf::Quadrature; 2],
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output_conf: [Conf::InPhase, Conf::Quadrature],
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}
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}
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}
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@ -137,7 +157,7 @@ const APP: () = {
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c.resources.adcs.1.acquire_buffer(),
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];
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let dac_samples = [
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let mut dac_samples = [
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c.resources.dacs.0.acquire_buffer(),
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c.resources.dacs.1.acquire_buffer(),
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];
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@ -145,21 +165,37 @@ const APP: () = {
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let lockin = c.resources.lockin;
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let settings = c.resources.settings;
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let timestamp =
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c.resources.timestamper.latest_timestamp().unwrap_or(None); // Ignore data from timer capture overflows.
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let (pll_phase, pll_frequency) = c.resources.pll.update(
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timestamp.map(|t| t as i32),
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settings.pll_tc[0],
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settings.pll_tc[1],
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);
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let (reference_phase, reference_frequency) = match settings.lockin_mode
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{
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LockinMode::External => {
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let timestamp =
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c.resources.timestamper.latest_timestamp().unwrap_or(None); // Ignore data from timer capture overflows.
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let (pll_phase, pll_frequency) = c.resources.pll.update(
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timestamp.map(|t| t as i32),
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settings.pll_tc[0],
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settings.pll_tc[1],
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);
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(
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pll_phase,
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(pll_frequency
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>> design_parameters::SAMPLE_BUFFER_SIZE_LOG2)
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as i32,
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)
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}
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LockinMode::Internal => {
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// Reference phase and frequency are known.
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(
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1i32 << 30,
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1i32 << (32 - design_parameters::SAMPLE_BUFFER_SIZE_LOG2),
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)
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}
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};
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let sample_frequency = ((pll_frequency
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>> design_parameters::SAMPLE_BUFFER_SIZE_LOG2)
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as i32)
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.wrapping_mul(settings.lockin_harmonic);
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let sample_phase = settings
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.lockin_phase
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.wrapping_add(pll_phase.wrapping_mul(settings.lockin_harmonic));
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let sample_frequency =
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reference_frequency.wrapping_mul(settings.lockin_harmonic);
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let sample_phase = settings.lockin_phase.wrapping_add(
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reference_phase.wrapping_mul(settings.lockin_harmonic),
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);
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let output: Complex<i32> = adc_samples[0]
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.iter()
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.unwrap()
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* 2; // Full scale assuming the 2f component is gone.
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let output = [
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match settings.output_conf[0] {
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Conf::PowerPhase => output.abs_sqr() as _,
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Conf::FrequencyDiscriminator => (output.log2() << 24) as _,
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Conf::Quadrature => output.re,
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},
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match settings.output_conf[1] {
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Conf::PowerPhase => output.arg(),
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Conf::FrequencyDiscriminator => pll_frequency as _,
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Conf::Quadrature => output.im,
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},
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];
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// Convert to DAC data.
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for i in 0..dac_samples[0].len() {
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dac_samples[0][i] = (output[0] >> 16) as u16 ^ 0x8000;
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dac_samples[1][i] = (output[1] >> 16) as u16 ^ 0x8000;
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for (channel, samples) in dac_samples.iter_mut().enumerate() {
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for (i, sample) in samples.iter_mut().enumerate() {
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let value = match settings.output_conf[channel] {
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Conf::Magnitude => output.abs_sqr() as i32 >> 16,
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Conf::Phase => output.arg() >> 16,
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Conf::LogPower => (output.log2() << 24) as i32 >> 16,
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Conf::ReferenceFrequency => {
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reference_frequency as i32 >> 16
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}
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Conf::InPhase => output.re >> 16,
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Conf::Quadrature => output.im >> 16,
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Conf::Modulation => DAC_SEQUENCE[i] as i32,
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};
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*sample = value as u16 ^ 0x8000;
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}
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}
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}
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