lockin: merge sample_phase/frequency computation
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@ -29,7 +29,7 @@ const DAC_SEQUENCE: [i16; design_parameters::SAMPLE_BUFFER_SIZE] =
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enum Conf {
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Magnitude,
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Phase,
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PllFrequency,
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ReferenceFrequency,
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LogPower,
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InPhase,
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Quadrature,
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@ -165,50 +165,38 @@ const APP: () = {
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let lockin = c.resources.lockin;
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let settings = c.resources.settings;
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let mut pll_frequency = 0;
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let (sample_phase, sample_frequency) = match settings.lockin_mode {
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let (reference_phase, reference_frequency) = match settings.lockin_mode
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{
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LockinMode::External => {
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let timestamp =
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c.resources.timestamper.latest_timestamp().unwrap_or(None); // Ignore data from timer capture overflows.
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let (pll_phase, frequency) = c.resources.pll.update(
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let (pll_phase, pll_frequency) = c.resources.pll.update(
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timestamp.map(|t| t as i32),
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settings.pll_tc[0],
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settings.pll_tc[1],
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);
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pll_frequency = frequency;
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let sample_frequency = ((pll_frequency
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>> design_parameters::SAMPLE_BUFFER_SIZE_LOG2)
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as i32)
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.wrapping_mul(settings.lockin_harmonic);
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let sample_phase = settings.lockin_phase.wrapping_add(
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pll_phase.wrapping_mul(settings.lockin_harmonic),
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);
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(sample_phase, sample_frequency)
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(
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pll_phase,
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(pll_frequency
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>> design_parameters::SAMPLE_BUFFER_SIZE_LOG2)
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as i32,
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)
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}
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LockinMode::Internal => {
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// Reference phase and frequency are known.
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let pll_phase = 0i32;
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let pll_frequency =
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1i32 << (32 - design_parameters::SAMPLE_BUFFER_SIZE_LOG2);
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// Demodulation LO phase offset
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let phase_offset: i32 = 1 << 30;
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let sample_frequency = (pll_frequency as i32)
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.wrapping_mul(settings.lockin_harmonic);
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let sample_phase = phase_offset.wrapping_add(
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pll_phase.wrapping_mul(settings.lockin_harmonic),
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);
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(sample_phase, sample_frequency)
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(
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1i32 << 30,
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1i32 << (32 - design_parameters::SAMPLE_BUFFER_SIZE_LOG2),
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)
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}
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};
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let sample_frequency =
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reference_frequency.wrapping_mul(settings.lockin_harmonic);
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let sample_phase = settings.lockin_phase.wrapping_add(
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reference_phase.wrapping_mul(settings.lockin_harmonic),
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);
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let output: Complex<i32> = adc_samples[0]
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.iter()
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// Zip in the LO phase.
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@ -230,7 +218,9 @@ const APP: () = {
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Conf::Magnitude => output.abs_sqr() as i32 >> 16,
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Conf::Phase => output.arg() >> 16,
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Conf::LogPower => (output.log2() << 24) as i32 >> 16,
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Conf::PllFrequency => pll_frequency as i32 >> 16,
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Conf::ReferenceFrequency => {
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reference_frequency as i32 >> 16
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}
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Conf::InPhase => output.re >> 16,
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Conf::Quadrature => output.im >> 16,
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Conf::Modulation => DAC_SEQUENCE[i] as i32,
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