From b2cbc6791df6c9fcef2fbafd12f25b3cc59ed8f9 Mon Sep 17 00:00:00 2001 From: Ryan Summers Date: Wed, 20 Jan 2021 12:55:45 +0100 Subject: [PATCH] Restructuring --- Cargo.toml | 8 -------- src/bin/lockin.rs | 18 +++++------------- 2 files changed, 5 insertions(+), 21 deletions(-) diff --git a/Cargo.toml b/Cargo.toml index 64979a8..f4f90fa 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -75,11 +75,3 @@ opt-level = 3 debug = true lto = true codegen-units = 1 - -[[bin]] -name = "iir" -path = "src/iir.rs" - -[[bin]] -name = "lockin" -path = "src/lockin.rs" diff --git a/src/bin/lockin.rs b/src/bin/lockin.rs index 9de067e..6b07901 100644 --- a/src/bin/lockin.rs +++ b/src/bin/lockin.rs @@ -12,21 +12,13 @@ use rtic::cyccnt::{Instant, U32Ext}; use heapless::{consts::*, String}; -// The number of ticks in the ADC sampling timer. The timer runs at 100MHz, so the step size is -// equal to 10ns per tick. -// Currently, the sample rate is equal to: Fsample = 100/256 MHz = 390.625 KHz -const ADC_SAMPLE_TICKS: u16 = 256; - -// The desired ADC sample processing buffer size. -const SAMPLE_BUFFER_SIZE: usize = 8; - // A constant sinusoid to send on the DAC output. const DAC_SEQUENCE: [f32; 8] = [0.0, 0.707, 1.0, 0.707, 0.0, -0.707, -1.0, -0.707]; -#[macro_use] -mod server; -mod hardware; -use hardware::{Adc1Input, Dac0Output, Dac1Output, AFE0, AFE1}; +use stabilizer::{ + hardware::{self, Adc1Input, Dac0Output, Dac1Output, AFE0, AFE1}, + server +}; use dsp::iir; const SCALE: f32 = ((1 << 15) - 1) as f32; @@ -166,7 +158,7 @@ const APP: () = { } else { server.poll(socket, |req| { info!("Got request: {:?}", req); - route_request!(req, + stabilizer::route_request!(req, readable_attributes: [ "stabilizer/iir/state": (|| { let state = c.resources.iir_state.lock(|iir_state|