Merge pull request #234 from vertigo-designs/feature/multi-app-support
Feature/multi app support
This commit is contained in:
commit
a31c9a5a7a
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@ -12,20 +12,8 @@ use rtic::cyccnt::{Instant, U32Ext};
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use heapless::{consts::*, String};
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use heapless::{consts::*, String};
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// The number of ticks in the ADC sampling timer. The timer runs at 100MHz, so the step size is
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use stabilizer::{hardware, server};
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// equal to 10ns per tick.
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// Currently, the sample rate is equal to: Fsample = 100/256 MHz = 390.625 KHz
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const ADC_SAMPLE_TICKS: u16 = 256;
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// The desired ADC sample processing buffer size.
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const SAMPLE_BUFFER_SIZE: usize = 8;
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// The number of cascaded IIR biquads per channel. Select 1 or 2!
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const IIR_CASCADE_LENGTH: usize = 1;
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#[macro_use]
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mod server;
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mod hardware;
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use dsp::iir;
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use dsp::iir;
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use hardware::{Adc0Input, Adc1Input, Dac0Output, Dac1Output, AFE0, AFE1};
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use hardware::{Adc0Input, Adc1Input, Dac0Output, Dac1Output, AFE0, AFE1};
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@ -34,6 +22,9 @@ const SCALE: f32 = ((1 << 15) - 1) as f32;
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const TCP_RX_BUFFER_SIZE: usize = 8192;
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const TCP_RX_BUFFER_SIZE: usize = 8192;
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const TCP_TX_BUFFER_SIZE: usize = 8192;
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const TCP_TX_BUFFER_SIZE: usize = 8192;
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// The number of cascaded IIR biquads per channel. Select 1 or 2!
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const IIR_CASCADE_LENGTH: usize = 1;
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#[rtic::app(device = stm32h7xx_hal::stm32, peripherals = true, monotonic = rtic::cyccnt::CYCCNT)]
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#[rtic::app(device = stm32h7xx_hal::stm32, peripherals = true, monotonic = rtic::cyccnt::CYCCNT)]
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const APP: () = {
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const APP: () = {
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struct Resources {
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struct Resources {
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@ -162,7 +153,7 @@ const APP: () = {
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} else {
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} else {
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server.poll(socket, |req| {
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server.poll(socket, |req| {
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info!("Got request: {:?}", req);
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info!("Got request: {:?}", req);
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route_request!(req,
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stabilizer::route_request!(req,
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readable_attributes: [
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readable_attributes: [
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"stabilizer/iir/state": (|| {
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"stabilizer/iir/state": (|| {
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let state = c.resources.iir_state.lock(|iir_state|
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let state = c.resources.iir_state.lock(|iir_state|
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@ -0,0 +1,15 @@
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#![no_std]
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#[macro_use]
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extern crate log;
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pub mod hardware;
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pub mod server;
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// The number of ticks in the ADC sampling timer. The timer runs at 100MHz, so the step size is
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// equal to 10ns per tick.
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// Currently, the sample rate is equal to: Fsample = 100/256 MHz = 390.625 KHz
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const ADC_SAMPLE_TICKS: u16 = 256;
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// The desired ADC sample processing buffer size.
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const SAMPLE_BUFFER_SIZE: usize = 8;
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@ -1,14 +1,12 @@
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use heapless::{consts::*, String, Vec};
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use core::fmt::Write;
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use core::fmt::Write;
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use heapless::{consts::*, String, Vec};
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use serde::{Deserialize, Serialize};
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use serde::{Deserialize, Serialize};
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use serde_json_core::{de::from_slice, ser::to_string};
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use serde_json_core::{de::from_slice, ser::to_string};
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use super::iir;
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use smoltcp as net;
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use smoltcp as net;
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use dsp::iir;
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#[macro_export]
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macro_rules! route_request {
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macro_rules! route_request {
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($request:ident,
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($request:ident,
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readable_attributes: [$($read_attribute:tt: $getter:tt),*],
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readable_attributes: [$($read_attribute:tt: $getter:tt),*],
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