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pounder_test
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experiment with duplex adc xfers 

problematic because:

* in tsize=1 there needs to be a cstart
* in tsize=0 there is no mssi
This commit is contained in:
Robert Jördens 2019-03-20 19:08:31 +00:00
parent 984cef6a4c
commit a2265ab2d1
1 changed files with 19 additions and 23 deletions
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42
src/main.rs
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@ -183,7 +183,6 @@ fn rcc_pll_setup(rcc: &stm32::RCC, flash: &stm32::FLASH) {
} }
fn io_compensation_setup(syscfg: &stm32::SYSCFG) { fn io_compensation_setup(syscfg: &stm32::SYSCFG) {
// enable I/O compensation cell
syscfg.cccsr.modify(|_, w| syscfg.cccsr.modify(|_, w|
w.en().set_bit() w.en().set_bit()
.cs().clear_bit() .cs().clear_bit()
@ -224,8 +223,8 @@ fn gpio_setup(gpioa: &stm32::GPIOA, gpiob: &stm32::GPIOB, gpiod: &stm32::GPIOD,
.moder3().output() .moder3().output()
); );
gpiog.odr.modify(|_, w| gpiog.odr.modify(|_, w|
w.odr2().set_bit() w.odr2().clear_bit()
.odr3().set_bit() .odr3().clear_bit()
); );
// SCK: PG11 // SCK: PG11
@ -287,13 +286,13 @@ fn spi1_setup(spi1: &stm32::SPI1) {
.lsbfrst().clear_bit() .lsbfrst().clear_bit()
.master().set_bit() .master().set_bit()
.sp().bits(0) // motorola .sp().bits(0) // motorola
.comm().bits(0b10) // simplex receiver .comm().bits(0b00) // duplex
.ioswp().clear_bit() .ioswp().clear_bit()
.midi().bits(0) // master inter data idle .midi().bits(0) // master inter data idle
.mssi().bits(11) // master SS idle .mssi().bits(11) // master SS idle
}); });
spi1.cr2.modify(|_, w| unsafe { spi1.cr2.modify(|_, w| unsafe {
w.tsize().bits(1) w.tsize().bits(0)
}); });
spi1.cr1.write(|w| w.spe().set_bit()); spi1.cr1.write(|w| w.spe().set_bit());
} }
@ -367,31 +366,28 @@ fn main() -> ! {
let spi2 = dp.SPI2; let spi2 = dp.SPI2;
spi2_setup(&spi2); spi2_setup(&spi2);
// at least one SCK between EOT and CSTART
spi1.cr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << 9)) });
// at least one SCK between EOT and CSTART // at least one SCK between EOT and CSTART
spi2.cr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << 9)) }); spi2.cr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << 9)) });
let txdr = &spi2.txdr as *const _ as *mut u16; // needs to be a half word write
let rxdr = &spi1.rxdr as *const _ as *const u16; let txdr1 = &spi1.txdr as *const _ as *mut u16;
let rxdr1 = &spi1.rxdr as *const _ as *const u16;
// needs to be a half word write
let txdr2 = &spi2.txdr as *const _ as *mut u16;
loop { loop {
#[cfg(feature = "bkpt")] #[cfg(feature = "bkpt")]
cortex_m::asm::bkpt(); cortex_m::asm::bkpt();
// at least one SCK between EOT and CSTART while spi1.sr.read().txp().bit_is_clear() {}
spi1.cr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << 9)) }); unsafe { ptr::write_volatile(txdr1, 0) };
while spi1.sr.read().eot().bit_is_clear() {} // while spi1.sr.read().txc().bit_is_clear() {}
spi1.ifcr.write(|w| w.eotc().set_bit()); while spi1.sr.read().rxp().bit_is_clear() {}
if spi1.sr.read().rxp().bit_is_clear() { let a = unsafe { ptr::read_volatile(rxdr1) };
continue; while spi2.sr.read().txp().bit_is_clear() {}
} unsafe { ptr::write_volatile(txdr2, a ^ 0x8000) };
let a = unsafe { ptr::read_volatile(rxdr) }; // while spi2.sr.read().txc().bit_is_clear() {}
let d = a ^ 0x8000;
if spi2.sr.read().txp().bit_is_clear() {
continue;
}
// needs to be a half word write
unsafe { ptr::write_volatile(txdr, d) };
while spi2.sr.read().txc().bit_is_clear() {}
#[cfg(feature = "bkpt")] #[cfg(feature = "bkpt")]
cortex_m::asm::bkpt(); cortex_m::asm::bkpt();