diff --git a/src/main.rs b/src/main.rs
index 92f4a8e..37d426f 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -183,7 +183,6 @@ fn rcc_pll_setup(rcc: &stm32::RCC, flash: &stm32::FLASH) {
 }
 
 fn io_compensation_setup(syscfg: &stm32::SYSCFG) {
-    // enable I/O compensation cell
     syscfg.cccsr.modify(|_, w|
         w.en().set_bit()
          .cs().clear_bit()
@@ -224,8 +223,8 @@ fn gpio_setup(gpioa: &stm32::GPIOA, gpiob: &stm32::GPIOB, gpiod: &stm32::GPIOD,
          .moder3().output()
     );
     gpiog.odr.modify(|_, w|
-        w.odr2().set_bit()
-         .odr3().set_bit()
+        w.odr2().clear_bit()
+         .odr3().clear_bit()
     );
 
     // SCK: PG11
@@ -287,13 +286,13 @@ fn spi1_setup(spi1: &stm32::SPI1) {
          .lsbfrst().clear_bit()
          .master().set_bit()
          .sp().bits(0)  // motorola
-         .comm().bits(0b10)  // simplex receiver
+         .comm().bits(0b00)  // duplex
          .ioswp().clear_bit()
          .midi().bits(0)  // master inter data idle
          .mssi().bits(11)  // master SS idle
     });
     spi1.cr2.modify(|_, w| unsafe {
-        w.tsize().bits(1)
+        w.tsize().bits(0)
     });
     spi1.cr1.write(|w| w.spe().set_bit());
 }
@@ -367,31 +366,28 @@ fn main() -> ! {
     let spi2 = dp.SPI2;
     spi2_setup(&spi2);
 
+    // at least one SCK between EOT and CSTART
+    spi1.cr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << 9)) });
     // at least one SCK between EOT and CSTART
     spi2.cr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << 9)) });
 
-    let txdr = &spi2.txdr as *const _ as *mut u16;
-    let rxdr = &spi1.rxdr as *const _ as *const u16;
+    // needs to be a half word write
+    let txdr1 = &spi1.txdr as *const _ as *mut u16;
+    let rxdr1 = &spi1.rxdr as *const _ as *const u16;
+    // needs to be a half word write
+    let txdr2 = &spi2.txdr as *const _ as *mut u16;
     loop {
         #[cfg(feature = "bkpt")]
         cortex_m::asm::bkpt();
 
-        // at least one SCK between EOT and CSTART
-        spi1.cr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << 9)) });
-        while spi1.sr.read().eot().bit_is_clear() {}
-        spi1.ifcr.write(|w| w.eotc().set_bit());
-        if spi1.sr.read().rxp().bit_is_clear() {
-            continue;
-        }
-        let a = unsafe { ptr::read_volatile(rxdr) };
-        let d = a ^ 0x8000;
-
-        if spi2.sr.read().txp().bit_is_clear() {
-            continue;
-        }
-        // needs to be a half word write
-        unsafe { ptr::write_volatile(txdr, d) };
-        while spi2.sr.read().txc().bit_is_clear() {}
+        while spi1.sr.read().txp().bit_is_clear() {}
+        unsafe { ptr::write_volatile(txdr1, 0) };
+        // while spi1.sr.read().txc().bit_is_clear() {}
+        while spi1.sr.read().rxp().bit_is_clear() {}
+        let a = unsafe { ptr::read_volatile(rxdr1) };
+        while spi2.sr.read().txp().bit_is_clear() {}
+        unsafe { ptr::write_volatile(txdr2, a ^ 0x8000) };
+        // while spi2.sr.read().txc().bit_is_clear() {}
 
         #[cfg(feature = "bkpt")]
         cortex_m::asm::bkpt();