Adding updates after review
This commit is contained in:
parent
2b6e6f59a4
commit
9e7bfd4371
|
@ -56,7 +56,7 @@ pub fn calculate_timestamp_timer_period() -> u32 {
|
||||||
// period of the timestamp timer. The period is always 1 larger than the value configured in the
|
// period of the timestamp timer. The period is always 1 larger than the value configured in the
|
||||||
// register.
|
// register.
|
||||||
let period: u64 = batch_duration_ticks * j - 1u64;
|
let period: u64 = batch_duration_ticks * j - 1u64;
|
||||||
assert!(period < u32::MAX as u64);
|
assert!(period <= u32::MAX as u64);
|
||||||
|
|
||||||
period as u32
|
period as u32
|
||||||
}
|
}
|
||||||
|
|
|
@ -677,10 +677,11 @@ const APP: () = {
|
||||||
);
|
);
|
||||||
|
|
||||||
// Ensure that we have enough time for an IO-update every sample.
|
// Ensure that we have enough time for an IO-update every sample.
|
||||||
let sample_frequency = (design_parameters::TIMER_FREQUENCY.0
|
let sample_frequency = {
|
||||||
as f32
|
let timer_frequency: hal::time::Hertz =
|
||||||
* 1_000_000.0)
|
design_parameters::TIMER_FREQUENCY.into();
|
||||||
/ ADC_SAMPLE_TICKS as f32;
|
timer_frequency.0 as f32 / ADC_SAMPLE_TICKS as f32
|
||||||
|
};
|
||||||
|
|
||||||
let sample_period = 1.0 / sample_frequency;
|
let sample_period = 1.0 / sample_frequency;
|
||||||
assert!(
|
assert!(
|
||||||
|
|
|
@ -152,19 +152,22 @@ macro_rules! timer_channels {
|
||||||
// Only atomic operations on completed on the timer registers.
|
// Only atomic operations on completed on the timer registers.
|
||||||
let regs = unsafe { &*<$TY>::ptr() };
|
let regs = unsafe { &*<$TY>::ptr() };
|
||||||
let sr = regs.sr.read();
|
let sr = regs.sr.read();
|
||||||
let ccx = regs.[< ccr $index >].read();
|
|
||||||
|
|
||||||
let result = if sr.[< cc $index if >]().bit_is_set() {
|
let result = if sr.[< cc $index if >]().bit_is_set() {
|
||||||
regs.sr.modify(|_, w| w.[< cc $index if >]().clear_bit());
|
// Read the capture value. Reading the captured value clears the flag in the
|
||||||
|
// status register automatically.
|
||||||
|
let ccx = regs.[< ccr $index >].read();
|
||||||
Some(ccx.ccr().bits())
|
Some(ccx.ccr().bits())
|
||||||
} else {
|
} else {
|
||||||
None
|
None
|
||||||
};
|
};
|
||||||
|
|
||||||
// If there is an overcapture, return an error.
|
// Read SR again to check for a potential over-capture. If there is an
|
||||||
if sr.[< cc $index of >]().bit_is_clear() {
|
// overcapture, return an error.
|
||||||
|
if regs.sr.read().[< cc $index of >]().bit_is_clear() {
|
||||||
Ok(result)
|
Ok(result)
|
||||||
} else {
|
} else {
|
||||||
|
regs.sr.modify(|_, w| w.[< cc $index of >]().clear_bit());
|
||||||
Err(())
|
Err(())
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
Loading…
Reference in New Issue