From 9e7bfd4371d50323287044142d7fd2a4ec4d96c4 Mon Sep 17 00:00:00 2001
From: Ryan Summers <ryan.summers@vertigo-designs.com>
Date: Wed, 6 Jan 2021 12:24:09 +0100
Subject: [PATCH] Adding updates after review

---
 src/digital_input_stamper.rs |  2 +-
 src/main.rs                  |  9 +++++----
 src/timers.rs                | 11 +++++++----
 3 files changed, 13 insertions(+), 9 deletions(-)

diff --git a/src/digital_input_stamper.rs b/src/digital_input_stamper.rs
index 85f248f..910ae98 100644
--- a/src/digital_input_stamper.rs
+++ b/src/digital_input_stamper.rs
@@ -56,7 +56,7 @@ pub fn calculate_timestamp_timer_period() -> u32 {
     // period of the timestamp timer. The period is always 1 larger than the value configured in the
     // register.
     let period: u64 = batch_duration_ticks * j - 1u64;
-    assert!(period < u32::MAX as u64);
+    assert!(period <= u32::MAX as u64);
 
     period as u32
 }
diff --git a/src/main.rs b/src/main.rs
index 5979d90..a0430d5 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -677,10 +677,11 @@ const APP: () = {
                     );
 
                     // Ensure that we have enough time for an IO-update every sample.
-                    let sample_frequency = (design_parameters::TIMER_FREQUENCY.0
-                        as f32
-                        * 1_000_000.0)
-                        / ADC_SAMPLE_TICKS as f32;
+                    let sample_frequency = {
+                        let timer_frequency: hal::time::Hertz =
+                            design_parameters::TIMER_FREQUENCY.into();
+                        timer_frequency.0 as f32 / ADC_SAMPLE_TICKS as f32
+                    };
 
                     let sample_period = 1.0 / sample_frequency;
                     assert!(
diff --git a/src/timers.rs b/src/timers.rs
index 5ffbeaf..8d7d010 100644
--- a/src/timers.rs
+++ b/src/timers.rs
@@ -152,19 +152,22 @@ macro_rules! timer_channels {
                     // Only atomic operations on completed on the timer registers.
                     let regs = unsafe { &*<$TY>::ptr() };
                     let sr = regs.sr.read();
-                    let ccx = regs.[< ccr $index >].read();
 
                     let result = if sr.[< cc $index if >]().bit_is_set() {
-                        regs.sr.modify(|_, w| w.[< cc $index if >]().clear_bit());
+                        // Read the capture value. Reading the captured value clears the flag in the
+                        // status register automatically.
+                        let ccx = regs.[< ccr $index >].read();
                         Some(ccx.ccr().bits())
                     } else {
                         None
                     };
 
-                    // If there is an overcapture, return an error.
-                    if sr.[< cc $index of >]().bit_is_clear() {
+                    // Read SR again to check for a potential over-capture. If there is an
+                    // overcapture, return an error.
+                    if regs.sr.read().[< cc $index of >]().bit_is_clear() {
                         Ok(result)
                     } else {
+                        regs.sr.modify(|_, w| w.[< cc $index of >]().clear_bit());
                         Err(())
                     }
                 }