Adding documentation for ADCs and DACs
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src/adc.rs
81
src/adc.rs
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///! Stabilizer ADC management interface
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///!
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///! The Stabilizer ADCs utilize a DMA channel to trigger sampling. The SPI streams are configured
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///! for full-duplex operation, but only RX is connected to physical pins. A timer channel is
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///! configured to generate a DMA write into the SPI TXFIFO, which initiates a SPI transfer and
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///! results in an ADC sample read for both channels.
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///! # Design
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///!
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///! In order to read multiple samples without interrupting the CPU, a separate DMA transfer is
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///! configured to read from each of the ADC SPI RX FIFOs. Due to the design of the SPI peripheral,
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///! these DMA transfers stall when no data is available in the FIFO. Thus, the DMA transfer only
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///! completes after all samples have been read. When this occurs, a CPU interrupt is generated so
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///! that software can process the acquired samples from both ADCs. Only one of the ADC DMA streams
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///! is configured to generate an interrupt to handle both transfers, so it is necessary to ensure
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///! both transfers are completed before reading the data. This is usually not significant for
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///! busy-waiting because the transfers should complete at approximately the same time.
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///! Stabilizer ADCs are connected to the MCU via a simplex, SPI-compatible interface. The ADCs
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///! require a setup conversion time after asserting the CSn (convert) signal to generate the ADC
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///! code from the sampled level. Once the setup time has elapsed, the ADC data is clocked out of
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///! MISO. The internal setup time is managed by the SPI peripheral via a CSn setup time parameter
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///! during SPI configuration, which allows offloading the management of the setup time to hardware.
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///!
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///! Because of the SPI-compatibility of the ADCs, a single SPI peripheral + DMA is used to automate
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///! the collection of multiple ADC samples without requiring processing by the CPU, which reduces
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///! overhead and provides the CPU with more time for processing-intensive tasks, like DSP.
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///!
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///! The automation of sample collection utilizes two DMA streams, the SPI peripheral, and a timer
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///! compare channel for each ADC. The timer comparison channel is configured to generate a
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///! comparison event every time the timer is equal to a specific value. Each comparison then
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///! generates a DMA transfer event to write into the SPI TX buffer. Although the SPI is a simplex,
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///! RX-only interface, it is configured in full-duplex mode and the TX pin is left disconnected.
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///! This allows the SPI interface to periodically read a single word whenever a word is written to
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///! the TX side. Thus, by running a continuous DMA transfer to periodically write a value into the
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///! TX FIFO, we can schedule the regular collection of ADC samples in the SPI RX buffer.
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///!
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///! In order to collect the acquired ADC samples into a RAM buffer, a second DMA transfer is
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///! configured to read from the SPI RX FIFO into RAM. The request for this transfer is connected to
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///! the SPI RX data signal, so the SPI peripheral will request to move data into RAM whenever it is
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///! available. When enough samples have been collected, a transfer-complete interrupt is generated
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///! and the ADC samples are available for processing.
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///!
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///! The SPI peripheral internally has an 8- or 16-byte TX and RX FIFO, which corresponds to a 4- or
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///! 8-sample buffer for incoming ADC samples. During the handling of the DMA transfer completion,
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///! there is a small window where buffers are swapped over where it's possible that a sample could
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///! be lost. In order to avoid this, the SPI RX FIFO is effectively used as a "sample overflow"
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///! region and can buffer a number of samples until the next DMA transfer is configured. If a DMA
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///! transfer is still not set in time, the SPI peripheral will generate an input-overrun interrupt.
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///! This interrupt then serves as a means of detecting if samples have been lost, which will occur
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///! whenever data processing takes longer than the collection period.
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///!
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///!
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///! ## Starting Data Collection
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///!
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///! Because the DMA data collection is automated via timer count comparisons and DMA transfers, the
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///! ADCs can be initialized and configured, but will not begin sampling the external ADCs until the
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///! sampling timer is enabled. As such, the sampling timer should be enabled after all
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///! initialization has completed and immediately before the embedded processing loop begins.
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///!
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///!
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///! ## Batch Sizing
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///!
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///! The ADCs collect a group of N samples, which is referred to as a batch. The size of the batch
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///! is configured by the user at compile-time to allow for a custom-tailored implementation. Larger
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///! batch sizes generally provide for more processing time per sample, but come at the expense of
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///! increased input -> output latency.
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///!
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///!
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///! # Note
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///!
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///! While there are two ADCs, only a single ADC is configured to generate transfer-complete
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///! interrupts. This is done because it is assumed that the ADCs will always be sampled
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///! simultaneously. If only a single ADC is used, it must always be ADC0, as ADC1 will not generate
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///! transfer-complete interrupts.
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///!
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///! There is a very small amount of latency between sampling of ADCs due to bus matrix priority. As
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///! such, one of the ADCs will be sampled marginally earlier before the other because the DMA
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///! requests are generated simultaneously. This can be avoided by providing a known offset to the
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///! sample DMA requests, which can be completed by setting e.g. ADC0's comparison to a counter
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///! value of 0 and ADC1's comparison to a counter value of 1.
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///!
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///! In this implementation, single buffer mode DMA transfers are used because the SPI RX FIFO can
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///! be used as a means to both detect and buffer ADC samples during the buffer swap-over. Because
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///! of this, double-buffered mode does not offer any advantages over single-buffered mode (unless
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///! double-buffered mode offers less overhead when accessing data).
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use super::{
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hal, sampling_timer, DMAReq, DmaConfig, MemoryToPeripheral,
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PeripheralToMemory, Priority, TargetAddress, Transfer, SAMPLE_BUFFER_SIZE,
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75
src/dac.rs
75
src/dac.rs
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@ -1,8 +1,45 @@
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///! Stabilizer DAC management interface
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///!
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///! The Stabilizer DAC utilize a DMA channel to generate output updates. A timer channel is
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///! configured to generate a DMA write into the SPI TXFIFO, which initiates a SPI transfer and
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///! results in DAC update for both channels.
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///! # Design
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///!
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///! Stabilizer DACs are connected to the MCU via a simplex, SPI-compatible interface. Each DAC
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///! accepts a 16-bit output code.
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///!
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///! In order to maximize CPU processing time, the DAC code updates are offloaded to hardware using
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///! a timer compare channel, DMA stream, and the DAC SPI interface.
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///!
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///! The timer comparison channel is configured to generate a DMA request whenever the comparison
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///! occurs. Thus, whenever a comparison happens, a single DAC code can be written to the output. By
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///! configuring a DMA stream for a number of successive DAC codes, hardware can regularly update
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///! the DAC without requiring the CPU.
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///!
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///! ## Multiple Samples to Single DAC Codes
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///!
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///! For some applications, it may be desirable to generate a single DAC code from multiple ADC
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///! samples. In order to maintain timing characteristics between ADC samples and DAC code outputs,
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///! applications are required to generate one DAC code for each ADC sample. To accomodate mapping
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///! multiple inputs to a single output, the output code can be repeated a number of times in the
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///! output buffer corresponding with the number of input samples that were used to generate it.
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///!
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///!
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///! # Note
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///!
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///! There is a very small amount of latency between updating the two DACs due to bus matrix
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///! priority. As such, one of the DACs will be updated marginally earlier before the other because
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///! the DMA requests are generated simultaneously. This can be avoided by providing a known offset
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///! to other DMA requests, which can be completed by setting e.g. DAC0's comparison to a
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///! counter value of 2 and DAC1's comparison to a counter value of 3. This will have the effect of
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///! generating the DAC updates with a known latency of 1 timer tick to each other and prevent the
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///! DMAs from racing for the bus. As implemented, the DMA channels utilize natural priority of the
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///! DMA channels to arbitrate which transfer occurs first.
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///!
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///!
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///! # Future Improvements
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///!
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///! In this implementation, single buffer mode DMA transfers are used. As a result of this, it's
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///! possible that a timer comparison could be missed during the swap-over, which will result in a
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///! delay of a single output code. In the future, this can be remedied by utilize double-buffer
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///! mode for the DMA transfers.
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use super::{
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hal, sampling_timer, DMAReq, DmaConfig, MemoryToPeripheral, TargetAddress,
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Transfer, SAMPLE_BUFFER_SIZE,
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@ -90,12 +127,11 @@ macro_rules! dac_output {
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let mut spi = spi.disable();
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spi.listen(hal::spi::Event::Error);
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// Allow the SPI FIFOs to operate using only DMA data channels.
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spi.enable_dma_tx();
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// Enable SPI and start it in infinite transaction mode.
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spi.inner().cr1.modify(|_, w| w.spe().set_bit());
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spi.inner().cr1.modify(|_, w| w.cstart().started());
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// AXISRAM is uninitialized. As such, we manually zero-initialize it here before
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// starting the transfer.
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for byte in DAC_BUF[$index].iter_mut() {
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*byte = 0;
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}
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// Construct the trigger stream to write from memory to the peripheral.
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let transfer: Transfer<_, _, MemoryToPeripheral, _> =
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@ -108,6 +144,15 @@ macro_rules! dac_output {
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trigger_config,
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);
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transfer.start(|spi| {
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// Allow the SPI FIFOs to operate using only DMA data channels.
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spi.enable_dma_tx();
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// Enable SPI and start it in infinite transaction mode.
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spi.inner().cr1.modify(|_, w| w.spe().set_bit());
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spi.inner().cr1.modify(|_, w| w.cstart().started());
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});
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Self {
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transfer,
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// Note(unsafe): This buffer is only used once and provided for the next DMA transfer.
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@ -131,15 +176,9 @@ macro_rules! dac_output {
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&mut self,
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next_buffer: &'static mut [u16; SAMPLE_BUFFER_SIZE],
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) {
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// If the last transfer was not complete, we didn't write all our previous DAC codes.
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// Wait for all the DAC codes to get written as well.
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if self.first_transfer {
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self.first_transfer = false
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} else {
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// Note: If a device hangs up, check that this conditional is passing correctly, as
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// there is no time-out checks here in the interest of execution speed.
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while !self.transfer.get_transfer_complete_flag() {}
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}
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// Note: If a device hangs up, check that this conditional is passing correctly, as
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// there is no time-out checks here in the interest of execution speed.
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while !self.transfer.get_transfer_complete_flag() {}
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// Start the next transfer.
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self.transfer.clear_interrupts();
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