268 lines
14 KiB
Rust
268 lines
14 KiB
Rust
///! Stabilizer ADC management interface
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///!
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///! # Design
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///!
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///! Stabilizer ADCs are connected to the MCU via a simplex, SPI-compatible interface. The ADCs
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///! require a setup conversion time after asserting the CSn (convert) signal to generate the ADC
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///! code from the sampled level. Once the setup time has elapsed, the ADC data is clocked out of
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///! MISO. The internal setup time is managed by the SPI peripheral via a CSn setup time parameter
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///! during SPI configuration, which allows offloading the management of the setup time to hardware.
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///!
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///! Because of the SPI-compatibility of the ADCs, a single SPI peripheral + DMA is used to automate
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///! the collection of multiple ADC samples without requiring processing by the CPU, which reduces
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///! overhead and provides the CPU with more time for processing-intensive tasks, like DSP.
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///!
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///! The automation of sample collection utilizes two DMA streams, the SPI peripheral, and a timer
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///! compare channel for each ADC. The timer comparison channel is configured to generate a
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///! comparison event every time the timer is equal to a specific value. Each comparison then
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///! generates a DMA transfer event to write into the SPI TX buffer. Although the SPI is a simplex,
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///! RX-only interface, it is configured in full-duplex mode and the TX pin is left disconnected.
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///! This allows the SPI interface to periodically read a single word whenever a word is written to
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///! the TX side. Thus, by running a continuous DMA transfer to periodically write a value into the
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///! TX FIFO, we can schedule the regular collection of ADC samples in the SPI RX buffer.
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///!
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///! In order to collect the acquired ADC samples into a RAM buffer, a second DMA transfer is
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///! configured to read from the SPI RX FIFO into RAM. The request for this transfer is connected to
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///! the SPI RX data signal, so the SPI peripheral will request to move data into RAM whenever it is
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///! available. When enough samples have been collected, a transfer-complete interrupt is generated
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///! and the ADC samples are available for processing.
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///!
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///! The SPI peripheral internally has an 8- or 16-byte TX and RX FIFO, which corresponds to a 4- or
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///! 8-sample buffer for incoming ADC samples. During the handling of the DMA transfer completion,
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///! there is a small window where buffers are swapped over where it's possible that a sample could
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///! be lost. In order to avoid this, the SPI RX FIFO is effectively used as a "sample overflow"
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///! region and can buffer a number of samples until the next DMA transfer is configured. If a DMA
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///! transfer is still not set in time, the SPI peripheral will generate an input-overrun interrupt.
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///! This interrupt then serves as a means of detecting if samples have been lost, which will occur
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///! whenever data processing takes longer than the collection period.
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///!
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///!
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///! ## Starting Data Collection
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///!
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///! Because the DMA data collection is automated via timer count comparisons and DMA transfers, the
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///! ADCs can be initialized and configured, but will not begin sampling the external ADCs until the
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///! sampling timer is enabled. As such, the sampling timer should be enabled after all
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///! initialization has completed and immediately before the embedded processing loop begins.
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///!
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///!
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///! ## Batch Sizing
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///!
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///! The ADCs collect a group of N samples, which is referred to as a batch. The size of the batch
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///! is configured by the user at compile-time to allow for a custom-tailored implementation. Larger
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///! batch sizes generally provide for more processing time per sample, but come at the expense of
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///! increased input -> output latency.
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///!
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///!
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///! # Note
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///!
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///! While there are two ADCs, only a single ADC is configured to generate transfer-complete
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///! interrupts. This is done because it is assumed that the ADCs will always be sampled
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///! simultaneously. If only a single ADC is used, it must always be ADC0, as ADC1 will not generate
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///! transfer-complete interrupts.
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///!
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///! There is a very small amount of latency between sampling of ADCs due to bus matrix priority. As
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///! such, one of the ADCs will be sampled marginally earlier before the other because the DMA
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///! requests are generated simultaneously. This can be avoided by providing a known offset to the
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///! sample DMA requests, which can be completed by setting e.g. ADC0's comparison to a counter
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///! value of 0 and ADC1's comparison to a counter value of 1.
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///!
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///! In this implementation, single buffer mode DMA transfers are used because the SPI RX FIFO can
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///! be used as a means to both detect and buffer ADC samples during the buffer swap-over. Because
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///! of this, double-buffered mode does not offer any advantages over single-buffered mode (unless
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///! double-buffered mode offers less overhead when accessing data).
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use super::{
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hal, sampling_timer, DMAReq, DmaConfig, MemoryToPeripheral,
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PeripheralToMemory, Priority, TargetAddress, Transfer, SAMPLE_BUFFER_SIZE,
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};
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// The following data is written by the timer ADC sample trigger into each of the SPI TXFIFOs. Note
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// that because the SPI MOSI line is not connected, this data is dont-care. Data in AXI SRAM is not
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// initialized on boot, so the contents are random.
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#[link_section = ".axisram.buffers"]
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static mut SPI_START: [u16; 1] = [0x00];
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// The following global buffers are used for the ADC sample DMA transfers. Two buffers are used for
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// each transfer in a ping-pong buffer configuration (one is being acquired while the other is being
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// processed). Note that the contents of AXI SRAM is uninitialized, so the buffer contents on
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// startup are undefined. The dimensions are `ADC_BUF[adc_index][ping_pong_index][sample_index]`.
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#[link_section = ".axisram.buffers"]
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static mut ADC_BUF: [[[u16; SAMPLE_BUFFER_SIZE]; 2]; 2] =
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[[[0; SAMPLE_BUFFER_SIZE]; 2]; 2];
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macro_rules! adc_input {
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($name:ident, $index:literal, $trigger_stream:ident, $data_stream:ident,
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$spi:ident, $trigger_channel:ident, $dma_req:ident) => {
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/// $spi is used as a type for indicating a DMA transfer into the SPI TX FIFO
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/// whenever the tim2 update dma request occurs.
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struct $spi {
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_channel: sampling_timer::tim2::$trigger_channel,
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}
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impl $spi {
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pub fn new(
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_channel: sampling_timer::tim2::$trigger_channel,
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) -> Self {
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Self { _channel }
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}
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}
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// Note(unsafe): This structure is only safe to instantiate once. The DMA request is hard-coded and
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// may only be used if ownership of the timer2 $trigger_channel compare channel is assured, which is
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// ensured by maintaining ownership of the channel.
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unsafe impl TargetAddress<MemoryToPeripheral> for $spi {
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/// SPI is configured to operate using 16-bit transfer words.
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type MemSize = u16;
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/// SPI DMA requests are generated whenever TIM2 CHx ($dma_req) comparison occurs.
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const REQUEST_LINE: Option<u8> = Some(DMAReq::$dma_req as u8);
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/// Whenever the DMA request occurs, it should write into SPI's TX FIFO to start a DMA
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/// transfer.
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fn address(&self) -> u32 {
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// Note(unsafe): It is assumed that SPI is owned by another DMA transfer and this DMA is
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// only used for the transmit-half of DMA.
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let regs = unsafe { &*hal::stm32::$spi::ptr() };
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®s.txdr as *const _ as u32
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}
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}
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/// Represents data associated with ADC.
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pub struct $name {
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next_buffer: Option<&'static mut [u16; SAMPLE_BUFFER_SIZE]>,
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transfer: Transfer<
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hal::dma::dma::$data_stream<hal::stm32::DMA1>,
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hal::spi::Spi<hal::stm32::$spi, hal::spi::Disabled, u16>,
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PeripheralToMemory,
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&'static mut [u16; SAMPLE_BUFFER_SIZE],
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>,
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_trigger_transfer: Transfer<
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hal::dma::dma::$trigger_stream<hal::stm32::DMA1>,
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$spi,
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MemoryToPeripheral,
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&'static mut [u16; 1],
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>,
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}
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impl $name {
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/// Construct the ADC input channel.
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///
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/// # Args
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/// * `spi` - The SPI interface used to communicate with the ADC.
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/// * `trigger_stream` - The DMA stream used to trigger each ADC transfer by writing a word into
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/// the SPI TX FIFO.
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/// * `data_stream` - The DMA stream used to read samples received over SPI into a data buffer.
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/// * `_trigger_channel` - The ADC sampling timer output compare channel for read triggers.
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pub fn new(
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spi: hal::spi::Spi<hal::stm32::$spi, hal::spi::Enabled, u16>,
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trigger_stream: hal::dma::dma::$trigger_stream<
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hal::stm32::DMA1,
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>,
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data_stream: hal::dma::dma::$data_stream<hal::stm32::DMA1>,
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trigger_channel: sampling_timer::tim2::$trigger_channel,
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) -> Self {
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// Generate DMA events when an output compare of the timer hitting zero (timer roll over)
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// occurs.
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trigger_channel.listen_dma();
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trigger_channel.to_output_compare(0);
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// The trigger stream constantly writes to the TX FIFO using a static word (dont-care
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// contents). Thus, neither the memory or peripheral address ever change. This is run in
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// circular mode to be completed at every DMA request.
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let trigger_config = DmaConfig::default()
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.priority(Priority::High)
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.circular_buffer(true);
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// Construct the trigger stream to write from memory to the peripheral.
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let mut trigger_transfer: Transfer<
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_,
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_,
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MemoryToPeripheral,
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_,
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> = Transfer::init(
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trigger_stream,
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$spi::new(trigger_channel),
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// Note(unsafe): Because this is a Memory->Peripheral transfer, this data is never
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// actually modified. It technically only needs to be immutably borrowed, but the
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// current HAL API only supports mutable borrows.
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unsafe { &mut SPI_START },
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None,
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trigger_config,
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);
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// The data stream constantly reads from the SPI RX FIFO into a RAM buffer. The peripheral
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// stalls reads of the SPI RX FIFO until data is available, so the DMA transfer completes
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// after the requested number of samples have been collected. Note that only ADC1's (sic!)
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// data stream is used to trigger a transfer completion interrupt.
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let data_config = DmaConfig::default()
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.memory_increment(true)
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.transfer_complete_interrupt($index == 1)
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.priority(Priority::VeryHigh);
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// A SPI peripheral error interrupt is used to determine if the RX FIFO overflows. This
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// indicates that samples were dropped due to excessive processing time in the main
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// application (e.g. a second DMA transfer completes before the first was done with
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// processing). This is used as a flow control indicator to guarantee that no ADC samples
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// are lost.
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let mut spi = spi.disable();
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spi.listen(hal::spi::Event::Error);
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// The data transfer is always a transfer of data from the peripheral to a RAM buffer.
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let mut data_transfer: Transfer<_, _, PeripheralToMemory, _> =
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Transfer::init(
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data_stream,
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spi,
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// Note(unsafe): The ADC_BUF[$index][0] is "owned" by this peripheral.
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// It shall not be used anywhere else in the module.
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unsafe { &mut ADC_BUF[$index][0] },
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None,
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data_config,
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);
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data_transfer.start(|spi| {
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// Allow the SPI FIFOs to operate using only DMA data channels.
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spi.enable_dma_rx();
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spi.enable_dma_tx();
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// Enable SPI and start it in infinite transaction mode.
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spi.inner().cr1.modify(|_, w| w.spe().set_bit());
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spi.inner().cr1.modify(|_, w| w.cstart().started());
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});
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trigger_transfer.start(|_| {});
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Self {
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// Note(unsafe): The ADC_BUF[$index][1] is "owned" by this peripheral. It shall not be used
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// anywhere else in the module.
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next_buffer: unsafe { Some(&mut ADC_BUF[$index][1]) },
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transfer: data_transfer,
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_trigger_transfer: trigger_transfer,
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}
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}
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/// Obtain a buffer filled with ADC samples.
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///
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/// # Returns
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/// A reference to the underlying buffer that has been filled with ADC samples.
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pub fn acquire_buffer(&mut self) -> &[u16; SAMPLE_BUFFER_SIZE] {
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// Wait for the transfer to fully complete before continuing.
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// Note: If a device hangs up, check that this conditional is passing correctly, as there is
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// no time-out checks here in the interest of execution speed.
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while !self.transfer.get_transfer_complete_flag() {}
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let next_buffer = self.next_buffer.take().unwrap();
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// Start the next transfer.
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self.transfer.clear_interrupts();
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let (prev_buffer, _) =
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self.transfer.next_transfer(next_buffer).unwrap();
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self.next_buffer.replace(prev_buffer); // .unwrap_none() https://github.com/rust-lang/rust/issues/62633
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self.next_buffer.as_ref().unwrap()
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}
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}
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};
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}
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adc_input!(Adc0Input, 0, Stream0, Stream1, SPI2, Channel1, TIM2_CH1);
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adc_input!(Adc1Input, 1, Stream2, Stream3, SPI3, Channel2, TIM2_CH2);
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